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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1

A 26-G Input-Impedance 112-dB Dynamic-Range

Two-Step Direct-Conversion Front-End With
Improved 1-Modulation for Wearable
Biopotential Acquisition
Yuzhi Hao , Hua Fan , Member, IEEE, Yong Lian , Fellow, IEEE, and Mingyi Chen , Senior Member, IEEE

Abstract— This article presents a high dynamic range (DR) wearable devices normally acquire bio-potentials through the
direct conversion front-end (Direct-FE) IC enabling the wearable skull, skeleton, muscle, or skin, which brings a major obstacle
acquisition of weak bio-potentials superposed onto large motion for medical-standard recordings. The environmental interfer-
artifacts (MAs). The prototype IC has been fabricated in a
standard 0.18-µm CMOS process. Benefiting from the proposed ence, such as motion artifacts (MAs) or mains interference
feedback (FB) two-step direct conversion architecture with an (MI) at 50/60 Hz, normally has a much higher amplitude than
improved 1-modulation, as well as a novel differential differ- the weak bio-potentials. For instance, EEG signals generally
ence amplifier (DDA) and a dynamic-element-matching (DEM) have an amplitude in the range of µV–mV, while MAs caused
technique, it achieves a peak input range of 3.56 VPP , an input- by skin expansion or muscle contraction could be up to
referred noise (IRN) of 2.2 µVrms , an input impedance of 26 G,
and a ±1.8-V electrode dc offset (EDO) tolerance, while consum- tens of mV [7]. Dry or non-contact electrodes could present
ing only 63-µW power. Compared with state-of-the-art Direct- even higher MAs or MI due to the impedance mismatch
FEs, the proposed work demonstrates an advanced DR (112 dB) of the electrodes [8], [9]. In extreme scenarios, MAs could
and a competitive FOMDR (175 dB). The prototype IC has be possibly up to hundreds of mV, which might saturate
been validated based on in vivo experiments, demonstrating its the entire analog front-end (AFE). Therefore, the dynamic
capability for artifact-tolerant wearable bio-potential acquisition.
range (DR) of the AFE should be sufficiently high to accom-
Index Terms— Artifact-tolerant, bio-potential acquisition, modate small bio-potentials superposed onto large artifacts.
direct conversion front-end (Direct-FE), dynamic range (DR),
As illustrated in Fig. 1, the amplitude of the artifacts could
input impedance, wearable.
typically be over 100 dB stronger than the bio-potentials,
I. I NTRODUCTION leading to a corresponding requirement of more than 100-dB
DR. For instance, TI’s ADS1299 has a DR of 125 dB [10],
W EARABLE biomedical devices have become increas-
ingly popular in recent decades, enabling real-time
monitoring of various kinds of bio-potentials, such as
which is necessary to withstand large MAs in wearable EEG
monitoring. In addition to DR, input impedance is another
electroencephalogram (EEG), electrocardiogram (ECG), and critical specification for wearable devices. The skin–electrode
electromyography (EMG) [1], [2], [3], [4], [5], [6]. Unlike interface could simply be modeled by a capacitor (typically
implantable devices, the miniature, portable, and comfortable from 10 pF to 200 nF) in parallel with a resistor (typically
from 1 G to infinity, depending on the interface material)
Received 13 June 2024; revised 2 September 2024 and 4 November 2024; [11]. In wearable devices, as the impedance of the dry or
accepted 6 December 2024. This article was approved by Associate Editor
Nick van Helleputte. This work was supported in part by the National Key non-contact electrode is extremely high, a much higher input
Research and Development Program of China under Grant 2021YFF1200601 impedance (at least up to G range within the bio-potential
and in part by the National Natural Science Foundation of China under Grant bandwidth) is required to improve the signal integrity and the
62174109. (Corresponding author: Mingyi Chen.)
This work involved human subjects or animals in its research. Approval common-mode rejection ratio (CMRR).
of all ethical and experimental procedures and protocols was granted by the To achieve high DR, conventional AFE typically consists of
National Population Health Data Center. a low-gain instrumentation amplifier (IA) followed by a high-
Yuzhi Hao and Mingyi Chen are with the National Key Laboratory of
Advanced Micro and Nano Manufacture Technology and the Department resolution ADC [12], [13], [14], [15], [16], [17]. The low-gain
of Micro/Nano Electronics, School of Electronic Information and Electrical IA normally operates under high supply voltage to get rid of
Engineering, Shanghai Jiao Tong University, Shanghai 200240, China (e-mail: the signal saturation, while the high-resolution ADC is used
[email protected]).
Hua Fan is with Shenzhen Institute for Advanced Study, University of to improve the signal-to-noise ratio (SNR). However, imple-
Electronic Science and Technology of China, Shenzhen 518000, China, and menting a high-resolution ADC leads to increasing power
also with the School of Integrated Circuit Science and Engineering (Exemplary dissipation, which could be a concern for wearable devices.
School of Microelectronics), University of Electronic Science and Technology
of China, Chengdu 611731, China. To further extend the DR, a programmable gain amplifier
Yong Lian is with the Department of EECS, York University, Toronto, (PGA) with automatic gain control (AGC) keeps the output
ON M3J 1P3, Canada. amplitude within a specific range [18]. However, the maximum
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/JSSC.2024.3514745. signal-to-noise-and-distortion ratio (SNDR) is fundamentally
Digital Object Identifier 10.1109/JSSC.2024.3514745 limited (47.3 dB) by the subsequent ADC. A 1–6 ADC with
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2 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 1. Frequency and amplitude of representative bio-potentials, interference

signals, and MAs.

flexible oversampling ratio (OSR) is proposed in [19]. The

OSR can be adjusted according to the gain of the PGA so that
a larger input range, as well as a smaller input-referred-noise
(IRN), could be simultaneously achieved to extend the DR.
However, the settling process during the gain adjustment
leads to a discontinuous and smooth-less signal recording.
Signal-folding techniques keep IA from saturation [20], [21],
[22]. With a signal-folding current DAC (I-DAC) at IA’s
input, a DR up to 96 dB is achieved [20]. However, the I-DAC
Fig. 2. Performance summary and comparison. (a) 1M [31], [32].
reduces the input impedance to several M while its noise (b) 1–16 M. (c) This work: two-step 1M.
is directly coupled to the input. A signal-folding amplifier
is proposed in [21], which is capable of accommodating
rail-to-rail input even with a gain of up to 17.8. However, impedance of 7.8 G, a 103.6-dB SNDR, and a 105-dB
the sample-and-hold (S/H) operation at the input results in DR. The dc-coupled Gm-C integrator improves the input
a low input impedance (∼100 M), while the noise folding impedance. However, the limited input range and electrode
effect cannot be well-addressed without an anti-aliasing filter. dc offset (EDO) tolerance are the existing major issues that
Recently, a continuous-time track-and-zoom (TAZ) technique need to be addressed. By incorporating other advanced spec-
has been proposed in [22]. The event-driven level-crossing trum shaping techniques, such as 1-modulation (1M) or
signal-folding technique enables significant DR extension 1–16-modulation (1–16 M), the Direct-FE demonstrates
and power consumption reduction. It achieves an input range superior DR than the conventional architecture, placing it
of 3.6 VPP and an IRN of 2.7 µVrms . However, the SNDR among the most promising candidates for wearable bio-
(<60 dB) is very limited due to the non-linearity and the potential acquisition. The Direct-FE with 1M was initially
noise of the feedback (FB) I-DAC. invented for multi-channel implantable recording due to its
The direct-conversion front-ends (Direct-FEs) have become compact dimensions and low power dissipation [30], [31],
a front-runner for artifact-tolerant bio-potential acquisition [32]. Nevertheless, its DR and SNDR are too limited for
AFEs in recent years [23], [24], [25], [26], [27], [28], [29], wearable devices, where large artifact-tolerant could be a main
[30], [31], [32], [33], [34], [35], [36], [37], [38]. Unlike concern [31], [32]. To improve the SNDR, 1–16 M has
conventional architecture (IA + ADC), the Direct-FE records been proposed later. The Direct-FE with 1–16 M achieves a
bio-potentials without a front-end amplifier. Larger artifacts 72.2-dB SNDR and a 1.13-µVrms IRN, while only consuming
could thus be accommodated as no gain stage is used. 630-nW power per channel [33]. However, the low input
Since the background noise typically is on the order of impedance (∼1 M) caused by the charging and discharging
10 µVrms [33], [39], the higher input-referred circuit noise of the input switched-capacitor could not well satisfy the
due to the lack of a front-end amplifier normally does not wearable devices. Other ac-coupled 1–16 M Direct-FEs also
matter a lot in real applications. Among the Direct-FEs, have insufficient input impedance for wearable devices [34],
the CT-16 M architecture exhibits good energy efficiency [35]. A dc-coupled second-order 1–16 M Direct-FE with
due to its high-order noise shaping [25], [26]. In [27], 11-G input impedance is presented in [36]. However, large
a Gm-C-based integrator achieves third-order noise shaping EDO might saturate the amplifier, while its linear input range
with a 91.3-dB SNDR. In [28], a Gm-C integrator and fundamentally limits the DR to 95.3 dB. Fig. 2 shows com-
a fully passive noise-shaping quantizer achieve an 83.7-dB parison of the advantages and drawbacks of different existing
DR at 10-kHz bandwidth. In [29], a pseudo-differential Direct-FE architectures. In conclusion, high input impedance
Gm-C integrator with embedded chopper achieves an input (up to G range) Direct-FEs with sufficient EDO-tolerance

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HAO et al.: 26-G INPUT-IMPEDANCE 112-dB DYNAMIC-RANGE TWO-STEP DIRECT-CONVERSION FRONT-END 3

and DR (over 100 dB) specifically oriented for wearable

devices are still lacking up to date.
The Direct-FEs could be implemented in the time domain
or VCO-based architectures as well. Thanks to the intrinsic
first-order noise shaping, the VCO-based ADCs have become
another popular candidate to obtain moderate DR with better
energy efficiency. An FB-controlled source degeneration is
applied to the input transconductor circuit using a resistor
digital-to-analog converter (R-DAC) [40], thereby mitigat-
ing the circuit nonlinearity while maintaining high input
impedance. It achieves an 81.3-dB SNDR and a 160-M
input impedance. In [41], a Gm-linearization technique has
been proposed that achieves a peak SNDR of 80.4 dB over
a 10-kHz bandwidth. The power consumption is 6.5 µW
while a high dc input impedance is achieved. To minimize the
signal swing before the Gm cell to improve linearity, a digital
pulse code modulation (DPCM) technique has been proposed
Fig. 3. (a) Conventional 1M. (b) Proposed improved 1M.
in [42]. It achieves 89.2-dB SNDR and 94.2-dB DR with a
power consumption of only 3.2 µW over a 500-Hz bandwidth.
However, the maximum input range (<300 mV) does not well inside the 6–1M loop could be easily saturated by large arti-
satisfy the wearable devices. In [43], a third-order VCO-based facts, blocking the small signal acquisition. To withstand large
ADC using a feedforward (FF) architecture achieves an input artifacts, 1M works in a different manner. It quantizes the dif-
range of 1.8 V with 92-dB DR, but its input impedance is ference between two consecutive samples, which approximates
limited to M range. In conclusion, the linearity issues of the derivation of the input signal. The so-called spectrum
the VCO-based Direct-FEs still require to be well-addressed equalization significantly improves the maximum input range,
to achieve over 100-dB DR. especially for input signals with extremely low changing rates.
To address the issues mentioned above, we propose a Fig. 3(a) shows the typical 1M, where an integrator is placed
two-step Direct-FE with improved 1M for wearable bio- in the FB loop. To compensate for the spectrum equalization
potential acquisition. The prototype achieves a peak input effect, the output requires another integrator to reconstruct
range of 3.56 VPP , an IRN of 2.2 µVrms , a DR of 112 dB, the input signal. As shown in (1), in the z-domain, the noise
an input impedance of 26 G, and a ±1.8-V electrode transfer function (NTF) and the signal transfer function (STF)
dc offset (EDO) tolerance. The performance mainly benefits are equal to unity. It is noteworthy that although the input
from three innovations: 1) a proposed FB two-step direct spectrum is equalized in the 1M, the quantization noise (E q )
conversion architecture, combining a 1M for coarse quan- is not shaped, which fundamentally limits its maximum SQNR
tization followed by a Nyquist ADC for fine quantization, to be the same as the quantizer
significantly extending the DR by 50 dB; 2) the use of an
improved 1M with large inter-stage gain, presenting higher STF1 (z) = 1, NTF1 (z) = 1. (1)
SNR, while alleviating the gain mismatch issue between The 6–1M with an inter-stage gain has been reported
the analog and digital domains; and 3) a novel differential in [35], [36], which reduces the IRN and thereby increases
difference amplifier (DDA) with ultrahigh input impedance the SNR. However, because of the reduced input range,
and a dynamic-element-matching (DEM) technique that deals the large inter-stage gain could not be adopted in 6–1M.
with the DAC’s mismatch and the gain error, leading to an Similarly, the SQNR of 1M could be improved by inserting
SNDR improvement by around 20 dB. an inter-stage gain as well, whereas a large gain could be
This article is structured as follows. Section II illustrates well-accommodated benefiting from a well-configured archi-
the architecture of the proposed Direct-FE. Specific design tecture. Fig. 3(b) shows the improved 1M with an inter-stage
considerations and tradeoffs are presented as well. Detailed gain, where A A and A D indicate the analog and digital gains,
circuit implementations are presented in Section III. The respectively. To obtain the same STF, it is essential that
measurement results are summarized and compared with state- A A /A D = 1. As shown in (2), the STF still equals to unity,
of-the-art works in Section IV, and Section V draws the whereas the NTF is ideally reduced to 1/A A so that large
conclusion. SQNR can be obtained. However, the mismatch between A A
II. P ROPOSED T WO -S TEP D IRECT-FE W ITH AN I MPROVED and A D introduces quantization noise leakage, which will be
1-M ODULATION discussed in Section II-B
AA
A. Improved 1-Modulation With an Inter-Stage Gain 1 AD =1
STF2 (z) = = 1
Prior Direct-FEs with 6–1M directly quantize the input
AA
AD
+ (1 − AA
AD
)Z −1
signal [27], [28], [29]. Benefiting from the large OSR and 1
AA
A =1 1
the high-order noise shaping, it can achieve a high signal- NTF2 (z) = h i D= . (2)
AA AA
+ (1 − AA
)Z −1 AA
to-quantization-noise ratio (SQNR). However, the integrator AD AD

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4 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 4. Magnitude of A A |1 − Z −1 | versus the normalized frequency with

increasing A A .

The inter-stage gain A A provides one more design parameter

in the improved 1M loop. As shown in (2), higher A A
effectively attenuates the quantization noise and thus improves Fig. 5. f IN_ max and SQNR versus A A with different quantization bits.
the SQNR. However, the maximum input frequency ( f IN_ max )
is inversely proportional to A A . This can be illustrated as 10
log π A3A .


follows. In the z-domain, the signal at node X can be expressed ≈n+ (7)
6.02
by
Therefore, in the improved 1M with an inter-stage gain,
X (z) = A A 1 − Z −1 VIN (z) − Z −1 E q (z).


(3) the ENOB can be increased not only through increasing the
It is noteworthy that the maximum output swing is funda- resolution of the quantizer but also through an increasing
mentally limited by the supply voltage (VDD ). Therefore, the A A . Each doubling of A A leads to a 1.5-bit improvement of
maximum input frequency without any saturation at node X ENOB, but at the cost of reducing maximum input frequency,
is calculated as follows: as indicated by (6) and (7). Fig. 5 shows plots of f IN_ max
(
max|X (z)| ≤ VDD and SQNR as a function of A A with different quantization
E q =0 bits. Theoretically, the improved 1M with an inter-stage gain
max|X (z)| = A A 1 − Z −1 VDD


is capable of achieving high DR through an optimized OSR
⇒ A A 1 − Z −1 ≤ 1. (4) and A A . The value of A A must be optimized to balance
several parameters, including SNR, power dissipation, FS , and
If the OSR is large, 1 − Z −1 can be simplified as
 π   π  FIN_ max . Increasing A A enhances SNR but at the same time
Z −1 = e− jωTS = cos − j sin reduces FIN_ max . Conversely, a smaller A A results in lower FS
OSR OSR and subsequently less power dissipation. In our design, A A
π
≈1− j is set to 85 to ensure that the Direct-FE achieves an SNR of
OSR
π 110 dB within a signal bandwidth of 125 Hz, while still main-
⇒ 1 − Z −1 = j (5) taining a good figure-of-merit (FoM). As an example, using a
OSR
where TS (=1/FS ) represents the sampling period, ω = 2π f IN , 6-bit quantizer with a 40-dB inter-stage gain, the ENOB can be
and f IN is the frequency of the input signal. Thus, we can up to 16.8 bits in theory, roughly corresponding over 100-dB
simplify the expression in (4) to DR. Nevertheless, the FB DAC in the 1M FB loop is at least
 required to have the same resolution as the final ENOB. Such
A Aπ  OSRmin = A A π a high-resolution DAC (>16 bit) is very difficult to implement
≤1⇒ FS (6) on-chip, particularly with a low OSR. Significant power-and-
OSR  f IN_ max = .
2π A A area overhead would be required to reduce the mismatch and
Therefore, with a certain A A and FS , one can obtain the min- the non-linearity. Consequently, the reported state-of-the-art
imum allowable OSR and thus the maximum input frequency. one-stage 1M Direct-FE normally has a limited ENOB of less
Fig. 4 shows plots of the magnitude of A A |1 − Z −1 | versus than 10 bits [31], [32]. To further improve the ENOB and the
the normalized frequency with increasing A A . As indicated DR of the improved 1M, we propose a two-step architecture
by (4), when A A increases from 1 to 128, the maximum in this work, which will be discussed in Section II-B.
allowable normalized input frequency reduces correspondingly
from 0.33 to 0.0025. If the noise is taken into account, f IN_ max
B. FB Two-Step Direct-FE With Improved 1M
is actually lower than the value indicated in (6). This impact
can be minimized by increasing the resolution of the quantizer. The ENOB and the DR of a 1M Direct-FE can be extended
As inferred by (2), the effective number of bits (ENOB) of by moving a step further to use a two-step architecture.
the improved 1M with an n-bit quantizer can be expressed Fig. 6(a) shows two typical configurations for the two-step
by (7). The equation can be simplified by substituting the OSR ADC. In the typical FF two-step ADC, the analog input is
obtained from (6) quantized by a coarse ADC (ADC1), while the residue is gen-
10 erated by a multiplying digital-to-analog converter (MDAC).
log OSR × A2A


ENOB1M = n + The residue is further quantized by another fine ADC (ADC2)
6.02
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HAO et al.: 26-G INPUT-IMPEDANCE 112-dB DYNAMIC-RANGE TWO-STEP DIRECT-CONVERSION FRONT-END 5

Fig. 7. Total SQNR versus the gain mismatch of FF and FB architectures.

Fig. 6. (a) Typical FF two-step ADC. (b) Proposed FB two-step Direct-FE

with improved 1M.

[44]. The outputs from ADC1 are multiplied by the inter-stage

gain and then added to the outputs from ADC2 in the digital
domain to construct the final outputs. In theory, if the analog
and digital gains (A A and A D ) are exactly matching, the
quantization error from the coarse quantizer (E q1 ) can be
totally eliminated. However, because of the gain mismatch
between A A and A D , a part of quantization noise E q1 leaks
to the final output (DOUT_FF ), which can be expressed by

DOUT_FF (z) = A D VIN (z) + (A D − A A )E q1 (z) + E q2 (z) (8)

where E q1 and E q2 are the quantization error from the coarse

and fine ADCs, respectively.
Borrowing the idea from the two-step ADC, we propose Fig. 8. (a) SQNR versus OSR with input amplitude = 0.45 full scale.
a two-step Direct-FE in our work. Different from the con- (b) SQNR versus input amplitude with OSR = 128.
ventional 1M architecture [31], [32], we use an improved
1M with an inter-stage gain as a coarse quantizer (ADC1), imately expressed by the following equations:
followed by a second stage of Nyquist ADC as a fine quantizer
(ADC2). Unlike the conventional FF two-step ADC, ADC1 is A D VIN
SQNRLFF ≈ 20 log
implemented in the FB loop, thus we name it as an FB two- (A D − A A )E q1
step Direct-FE. The integrator in the FB loop generates the VIN
= 20 log (11)
coarse quantization output, eliminating an extra reconstruction εE q1
integrator. The final output (DOUT_FB ) can be constructed by A A VIN
adding the results from ADC1 and ADC2. Therefore, in the SQNRLFB ≈ 20 log . (12)
ε Z −1 E q1
FB Direct-FE, DOUT_FB can be expressed by
Combining (11) and (12) leads to the following expression:
AA
DOUT_FB (z) = VIN (z)
1 + ε Z −1 SQNRLFB ≈ SQNRLFF + 20 log A A . (13)
εZ −1
− E q1 (z) + E q2 (z) (9) From (13), each doubling of the inter-stage gain (A A ) leads
1 + ε Z −1
to a 6-dB improvement of the SQNRL. Fig. 7 shows com-
where ε is the mismatch ratio between A A and A D parison of the total SQNR (including the leaked quantization
AA noise) versus the gain mismatch between the FF and FB
= 1 + ε. (10) architectures. The tolerance to gain mismatch is significantly
AD
improved in the proposed FB architecture. For example, with
From (8) and (9), the signal-to-leaked-quantization-noise the same SQNR target (100 dB), the FB architecture with a
ratio (SQNRL) in the FF and FB architectures can be approx- 3-bit quantizer improves gain-mismatch tolerance by 14×.

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6 IEEE JOURNAL OF SOLID-STATE CIRCUITS

C. Performance Comparison and Discussion the OSR obtained from (6)

To compare the performance of the presented two-step 10
log OSR × A2A


ENOB = m +
1M with the conventional 1M [31] and 1–16 M coun- 6.02
terparts [36] at the architecture level, extensive behavior 10
log π A3A .


≈m+ (14)
simulations have been implemented. 6.02
Fig. 8(a) shows the SQNR comparison of the conventional Comparing the above expression with (7), it is noteworthy
1M and 1–16 M architectures with the presented two- that the ENOB of the proposed two-step Direct-FE could be
step 1M architecture as a function of OSR. Although the eventually extended by increasing the resolution of the fine
SQNR gain of the presented 1M architecture has the same quantizer and the inter-stage gain (A A ). Corresponding to each
slope (3 dB/Octave) as the conventional 1M architecture, doubling of A A , the ENOB increases approximately by 1.5 bit.
over 50-dB SQNR improvement can be achieved because of Typically, when the circuit noise dominants the total noise, the
the two-step conversion that further extends the DR. Indeed, SNR and the ENOB (excluding distortion for simplicity) can
a second stage of Nyquist ADC is required to implement be expressed by
one more step of conversion, which inevitably introduces 2
X FS VDD
extra power and area overhead. However, the overall FoM, SNR = 10 log
2
, X FS =
including signal bandwidth, power dissipation, and SNDR, can 8Vrms 2
still be improved significantly. Our measurements (detailed in ⇒ ENOB = (SNR − 1.76)/6.02 (15)
Section IV) show that the peak SNDR is extended by over
where Vrms is the input-referred circuit noise, and X FS is
50 dB, while the power dissipation and area increase by 17%
the full-scale input range. The total SNR can therefore be
and 8%, respectively. As a result, the FoM has been approx-
calculated according to real circuit parameters based on (14)
imately enhanced by 50 dB. On the other hand, the 1–16
and (15). Targeting for over 16-bit ENOB, around 80% of the
architecture exhibits a 15-dB/Octave SQNR gain because of
noise budget is allocated to the circuit noise in our design.
the second-order noise shaping. However, the presented two-
step 1M architecture exhibits better SQNR for smaller OSR.
Given a fixed signal bandwidth, lower OSR and thereby lower III. C IRCUIT I MPLEMENTATION
sampling frequency could be used to achieve the same SQNR. Fig. 9(a) shows the architecture of the proposed two-step
Therefore, the presented architecture could potentially be more Direct-FE. The first stage implements coarse quantization
power-efficient than the 1–16 counterpart up to OSRs that with an improved 1M as discussed in Section II-A. The
SQNRs become comparable. second stage uses a 12-bit Nyquist SAR-ADC to quantize
Fig. 8(b) shows the SQNR comparison of the conven- the amplified residue and further extends the DR. We set
tional 1M and 1–16 M architectures with the presented f IN_ max to 125 Hz, as most of the artifacts that might cause
two-step 1M architecture as a function of the input ampli- saturation are within this frequency range. The low-pass DDA
tude. The presented architecture exhibits over 46-dB SQNR presents an anti-aliasing filtering for high-frequency inter-
improvement within the whole input range compared with the ference. To further suppress the high-frequency interference,
conventional 1M counterpart. The 1–16 M architecture has simple PCB-level RC low-pass filters could be added to the
almost the same SQNR for small input amplitude. However, input.
the maximum input amplitude is less because of the preceding Corresponding to the DR requirement, the inter-stage gain
gain stage (g = 2). Therefore, assuming the same IRN, A A is set to 85. An oversampling 2.5-bit flash-ADC quantizes
the presented architecture could have a higher DR than the the amplified residue (VOUT_DDA ). The output of the flash-ADC
1–16 counterpart. Besides, in applications without the need is integrated by an 8-bit up/down counter to obtain the coarse
for such a high DR, the second-stage Nyquist ADC could quantization results D1 . Then D1 drives an 8-bit C-DAC
be bypassed, recovering to the conventional 1M architecture including 255 unity capacitors (C1 –C255 ) to implement the
with reduced power dissipation. The flexibility that allows closed-loop 1M. Fig. 9(b) shows the circuit implementation of
for reconfiguration is an extra benefit compared with the the proposed C-DAC. The second-stage SAR-ADC quantizes
conventional single-loop 1–16 M architecture. VOUT_DDA and generates the results D2 . The digital outputs are
ultimately constructed by combining D1 and D2 . Segmenting
one stage of high-DR Direct-FE into a two-stage imple-
D. ENOB of the FB Two-Step Direct-FE mentation enables a significant reduction of power-and-area
overhead [36]. Although the conversion rate is correspondingly
The ideal ENOB of a conventional FF two-step ADC slower as a result of two-step sequential operations, this is
is approximately equal to the sum of the ENOB of each not a primary concern in the wearable devices as the signal
stage. Differently, in the proposed FB two-step Direct-FE bandwidth is low.
with improved 1M, the best ENOB can be obtained when
△ADC1 2n = △ADC2 2m , where n and m are the bit of the
coarse and fine ADCs, respectively, whereas △ADC1 and △ADC2 A. 1M Implementation
are the corresponding level of LSB, respectively. Ideally, Fig. 10(a) shows the schematic of the amplifier along with
the ENOB for the proposed FB two-step Direct-FE can be the FB C-DAC. For simplicity, only a single-ended version is
expressed by (14). It can be further simplified by substituting shown here, whereas the real implementation is a DDA (as

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HAO et al.: 26-G INPUT-IMPEDANCE 112-dB DYNAMIC-RANGE TWO-STEP DIRECT-CONVERSION FRONT-END 7

Fig. 9. (a) Architecture of the proposed two-step Direct-FE. (b) Detailed circuit implementation of the 8-bit C-DAC.

Similarly, when the output crosses the lower threshold

voltage VTL , the bottom plate of one C A is switched from
VREFH to VREFL . In this manner, the output voltage always stays
within the upper and lower thresholds so that voltage saturation
can be eliminated. In this design, VREFH and VREFL are VDD
and VSS , respectively. VDD is connected to the analog supply
voltage (VDD = 1.8 V), which is generated by an on-chip LDO.
VSS is connected to analog ground. This method reduces the
harmonic distortion caused by the nonlinear settling of the
internal reference voltage.
The ratio of C A to C F can be optimized according to the
sampling frequency (FS = 1/TS ) and VLSB . Given the maxi-
mum input frequency, a larger VLSB allows for a lower FS , thus
reducing the unity-gain-bandwidth (UGB) requirement of the
amplifier. However, if VLSB is set too large, the pulling-back
step might cause the output to cross both VTH and VTL . Conse-
quently, more switching cycles are needed before final settling,
Fig. 10. (a) Single-ended version of the DDA. (b) Output waveform of the
DDA with a ramping up input. resulting in an increased power dissipation. On the other hand,
the change of VOUT between two consecutive samplings should
always be less than VREF to prevent saturation. As a result, the
discussed in Section III-C). The inter-stage gain A A equals following equations need to be satisfied when optimizing C A
(N C A + C P )/C F + 1, where N indicates the number of and C F :
the unity-capacitor cells. Unlike conventional capacitively FB (
amplifiers, these capacitors are shared with the C-DAC by VREF ≤ VLSB ≤ VDD − 2VREF
(17)
switching the bottom plates to either VREFH or VREFL . The |△VOUT |max = 2π A A |VIN |max f IN_ max TS ≤ VREF
input signal VIN is isolated from the capacitor array, leading to
where |VIN |max = VDD /2. Accordingly, the ratio of C A /C F
an increasing input impedance. The parasitic capacitance C P
is set to 1/3 by solving (17). Therefore, the quantization step
affects the accuracy of A A . It mainly consists of the capaci-
VLSB of the C-DAC is equal to 1/3· VDD . With respect to VLSB ,
tance of the input pair (Cgg ) and the parasitic capacitance of
(6) can be rewritten as
the metal trace (CTrace ). Cgg can be effectively eliminated by
the proposed bootstrap circuit as described in Section III-C, 2VLSB FS
f IN_ max = . (18)
while CTrace can be minimized by shielding techniques [51]. VDD 2π A A
Fig. 10(b) illustrates the operation when VIN is slowly ramping Calculated from the above expression, the minimum sam-
up. Due to the 1M, when the output voltage crosses the upper pling frequency is approximately 100 kHz.
threshold voltage VTH , the bottom plate of one C A is switched
from VREFL to VREFH so that the output voltage is pulled back. B. Slope Detection and Output-Range Adaption
The pulling step of VOUT can be calculated by
Fig. 11(a) shows the slope detection circuit, which is
proposed to further reduce the minimum required sam-
CA pling frequency and thereby reduce the power consumption.
|△VOUT | = VLSB = (VREFH − VREFL ). (16)
CF Fig. 11(b) shows its operation flowchart. An asynchronous

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8 IEEE JOURNAL OF SOLID-STATE CIRCUITS

range is set between VSS and VTL . Conversely, if the input is

rapidly falling, the available output range is set between VDD
and VTH . The output range remains between VTH and VTL if
the input is changing slowly.
Compared with prior works [22], [30], which has a fixed
available output range, the adaptive output range enables a
flexible VLSB . Therefore, the minimum required sampling
frequency can be reduced accordingly. For example, if the
quantization step increases from VLSB to 2VLSB when the
input is rapidly changing, the minimum required sampling
frequency is reduced to 50 kHz according to (18). A flash-
ADC with higher resolution could be possibly used to
further improve the sensitivity of the slope detector but at
the expense of increasing power and area overhead. As an
optimum balance, we use a 2.5-bit flash-ADC (6-level) in
real implementation. The sampling frequency is ultimately
set to 60 kHz to leave sufficient margin for non-ideal factors,
such as the comparator’s noise and offset. The benefit of the
proposed method is that it reduces the required bandwidth
of the DDA so that the sampling frequency and thereby
the power dissipation could be significantly decreased.
In addition, it does not require any digital post-processing,
leading to a reduced systematic complexity.

C. Differential Difference Amplifier

Fig. 12(a) shows the schematic of the DDA circuit [45],
[46]. Our behavioral simulation shows that an open-loop gain
of at least 100 dB is required for the DDA. Therefore, we adopt
a gain-boosting two-stage OTA, with an open-loop gain close
to that of a three-stage amplifier. The loop stability can be
ensured by the miller compensation. Intuitively, the DDA can
be regarded as a combination of the two input amplifiers of
conventional three-opamp IA. As part of the bias current for
the two input amplifiers is shared in the DDA, the overall
power dissipation could be reduced. The input stage is a gain-
boosting folded-cascode amplifier, while a class-AB output
stage enhances the slew rate. To achieve a 0∼1.8-V input
range, the input stage is powered by an additional boosted
supply voltage. Compared with the complimentary input
stage [47], the crossover distortion can be minimized. Instead
of chopper stabilization, large-area transistors are adopted for
the input differential pair to minimize the 1/ f noise and
Fig. 11. (a) Schematic of the slope detection circuit and the comparator. the random offset. This ensures high input impedance while
(b) State flow diagram of the slope detection procedure. (c) Illustration of the getting rid of chopper ripples. To deal with the arising parasitic
output-range adaption technique.
capacitance due to large-area input differential pair, which
might increase harmonic distortion, we propose a bootstrap
clock CLKINT is generated to drive the 8-bit U/D counter when circuit, as shown in Fig. 12(b). MPa ’s parasitic overlap capac-
the flash-ADC has completed its comparison. Another 4-bit itance CGD is bootstrapped by the added transistor MPb .
counter is used to store the results obtained by comparing two To operate MPa and MPb simultaneously in the saturation
consecutive outputs (D1 and D1 Z −1 ). As shown in Fig. 11(b), region, it is necessary to satisfy the condition |VTH_MPb | <
the upper and lower threshold values were set to −3 and 3, |VG − VD1 | < |VTH_MPa |, where VTH_MPa and VTH_MPb are the
respectively. The counter value exceeds 3 when the input threshold voltage of MPa and MPb , respectively. An extra
signal is rapidly rising, while it falls below −3 when the transistor MPc is added to make use of the body effect
input signal is rapidly falling. On the other hand, the counter and reduce the threshold voltage of MPb . The sizes of the
value keeps within the upper and lower threshold values if input pMOS (MPa ) and bootstraps pMOS (MPb and MPc )
the input signal is changing slowly. Based on slope detection, are 1000µ/2µ, 10µ/0.5µ, and 2µ/0.5µ, respectively. Before
an output-range adaption technique is proposed. As shown in using the bootstrap technique, the simulated equivalent input
Fig. 11(c), if the input is rapidly rising, the available output parasitic capacitance is 324 fF, which is mainly dominant by
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HAO et al.: 26-G INPUT-IMPEDANCE 112-dB DYNAMIC-RANGE TWO-STEP DIRECT-CONVERSION FRONT-END 9

Fig. 12. (a) Detailed schematic of the DDA. (b) Input stage with a parasitic capacitor bootstrap structure.

CGD of MPa . After using the bootstrap, the remaining parasitic

is mainly contributed by the gate capacitance of MPb and
MPc , which is fairly small. Our simulation shows that the
equivalent input parasitic capacitance is reduced to 6.9 fF with
the bootstrap technique.
To achieve the corresponding settling accuracy of the
second-stage ADC, the following equation should be satisfied
in the two-step Direct-FE [44]:
gm Tsettle β
    
2 1 VDD
 Verror = VDD exp − ≤


3 CC 2 212 (19)
g m 1
= UGB = BW.


β

2πCC
where Tsettle is the allowable settling time for the DDA,
which is 11/12 · TS in our work. β is the FB factor, gm
is the transconductance of the DDA, and CC is the miller
compensation capacitance. Therefore, the minimum required
UGB of the DDA is calculated to be 8.6 MHz accordingly.

D. Data Weighted Averaging and Timing

To minimize the non-linear effect induced by the FB
C-DAC, we propose an improved DEM circuit. Unlike conven-
tional DEM which only handles C-DAC’s capacitor array [36],
Fig. 13. DDA output waveforms, timing diagrams, and the principle of the
the proposed DEM includes the FB capacitor C F as well. proposed DEM.
At each clock cycle, the unity-capacitor cells that comprise C F
are shifted, allowing the gain error to be shaped simultaneously in C A is switched from VSS to VDD to pull back the output.
with the C-DAC’s mismatch error, improving the linearity. The above operation is repeated at T [n + 2]. The capacitor
The 8-bit C-DAC includes a total amount of 85 C-DAC cells, switching is not implemented at T [n + 3] as the DDA’s output
as shown in Fig. 9(b). During its operation, the bottom plate is within the threshold. At T [n + 4], the DDA’s output is
of one C-DAC cell is connected to the output of the DDA. below the lower threshold. One capacitor in C A is switched
This C-DAC cell operates as the FB capacitor C F . While the from VDD to VSS to pull back the output. As the DEM’s
bottom plates of the other 84 C-DAC cells are connected to clock frequency is 60 kHz with a rotation period of 85 clock
the reference voltages (VDD or VSS , depending on the output of cycles, most of the C-DAC’s mismatch could be modulated
the decoder). These C-DAC cells operate as the amplification to 60 kHz/85 = 705 Hz, approximately 5.6 times the signal
capacitor C A . The DDA is configured into a non-inverting bandwidth (125 Hz), which can be easily filtered out.
amplifier, and therefore, the analog gain A A can be calculated
by A A = C A /C F + 1 = 85.
Fig. 13 illustrates a typical operation waveform of the DEM. E. ADC and Buffer
It operates as follows: At T [n], the FB capacitor C F consists A 2.5-bit flash-ADC is used as the coarse quantizer. The
of three unity capacitors, while the amplifier capacitor C A reference voltage (VREF1∼6 ) for flash-ADC is generated from
contains 252 capacitors. Half of C A are connected to VDD , VDD through a series resistor string as shown in Fig. 9(a).
whereas the other half are connected to VSS . At T [n + 1], A separate coarse quantizer is used instead of merging with
the DDA’s output exceeds the upper threshold. One capacitor the fine quantizer mainly because of several reasons. First, the
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10 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 14. Detailed implementation of the 12-bit SAR-ADC for fine quantiza-
tion. Fig. 15. (a) Die photograph with labeled blocks. (b) Power consumption
breakdown.

loop delay of the 1M needs to satisfy the setup and hold time
requirements. Under a certain sampling period TS , the delay
introduced by the coarse quantizer should thus be minimized
to allow sufficient time for the DDA’s settling process. The
adopted flash-ADC finishes the conversion within around
100 ns (under the worst case). Therefore, an adequate settling
time could be allocated to the DDA, which leads to a reduced
bandwidth and thereby a decreasing overall power dissipation.
Second, the 2.5-bit flash-ADC is implemented by only six
dynamic comparators, without adding too much hardware
complexity. Third, a separate coarse quantizer provides the fine
quantizer with the option to use different sampling frequency
Fig. 16. Measured transient response with large artifacts.
as an extra tradeoff. For example, use lower sampling fre-
quency to improve the overall energy efficiency, or use higher IV. M EASUREMENT R ESULTS
sampling frequency to increase the OSR and thus the SNR.
A 12-bit SAR-ADC is used as the fine quantizer to balance The Direct-FE IC has been fabricated with a stan-
the resolution and the power-and-area overhead. Fig. 14 shows dard 0.18-µm 1P3M CMOS process, occupying an area of
the schematic of the SAR-ADC. A segmented C-DAC is 2.25 mm2 . Fig. 15(a) shows the photograph of the prototype.
used. A standard binary-coded C-DAC is adopted for the 7-bit The power breakdown is shown in Fig. 15(b). The total power
MSBs, while a C-2C C-DAC is adopted for the 5-bit LSBs. consumption is 63 µW, including the ADC’s driving buffer.
The segmented C-DAC enables a significant reduction in the The DDA dominates the total power consumption. This is
overall area and complexity. One drawback is the C-DAC necessary because the IRN and linearity are mainly determined
in the 5-bit LSBs tends to have more parasitic capacitance, by the DDA. As the harmonic distortions are fundamentally
leading to increased harmonics distortion. Nevertheless, this limited by the matching accuracy of the C-DAC, a large
non-ideal effect can be effectively suppressed by a larger A A . capacitance value (70 pF) is used to improve its matching
In this work, we use top-plate sampling with MSB preset to accuracy. This leads to a satisfactory SNDR at the cost of
achieve full-range sampling without extra reset voltages [48]. a large chip area. A reduction in the capacitance might save
The SAR-ADC operates as follows: In the sampling phase, the chip area but increase harmonic distortion. Another possible
differential inputs are sampled on the top plates of the capac- solution is to use segmented-coding a data weighted averaging
itor array, and the MSB of the C-DACP is initially set to low, (DWA) [49], [50], which reduces the digital hardware, but
whereas the other bits are set to high. In the conversion phase, sacrifices the harmonics suppression.
the sampling switch is open and the comparator operates To validate the capability to tolerant large MAs and
correspondingly. If VDACP is higher than VDACN , the DAC bit the EDO, Fig. 16 shows the recording waveform of a
remains low. Otherwise, it is set to high. Then the second com- small sine-wave signal (5 mVPP ) superposed onto a large
parison begins. If VDACP is higher than VDACN , the DAC bit is square-wave signal (3.4 VPP ). The square-wave signal emu-
set to low. Otherwise, it remains high. The process goes so on lates large MAs or the time-variant EDO, which is around
and so forth until all the bits from MSB to LSB are set accord- third orders of magnitude stronger than the sine-wave signal.
ingly. The capacitors in C-DACN switch in a similar manner. The measured output tracks the artifacts in 2.06 ms without
A unity-gain buffer has been inserted between the DDA saturation. The tracking rate is fundamentally determined by
and the SAR-ADC, which contributes two benefits as follows. VLSB , which could be further improved by using the Radix-2
First, the load capacitance to be driven by the DDA can dynamic expansion technique [23], [32].
be reduced. Second, the buffer’s noise is suppressed by the Fig. 17 shows the measured differential-mode input
preceding DDA. Therefore, the overall power dissipation could impedance versus frequency. Due to the dc-coupled DDA,
be lower, while still satisfies the noise and the settling-time the input impedance is approximately up to 26 and 1.25 G,
requirements. at 0.5 and 50 Hz, respectively. Fig. 18 shows the measurement

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HAO et al.: 26-G INPUT-IMPEDANCE 112-dB DYNAMIC-RANGE TWO-STEP DIRECT-CONVERSION FRONT-END 11

Fig. 17. Measured differential-mode input impedance versus frequency. Fig. 20. PSD of reconstructed signals (DOUT ) w/ and w/o DEM.

Fig. 18. Input-impedance measurement setup.

Fig. 21. Measured SNDR/SNR versus input amplitude with 21.057-Hz input.

2) mismatch of the output load impedance Z L . Since Z B is

quite large at low frequency, the intrinsic CMRR is dominant
by the matching of gm . The Monte Carlo simulation shows
the standard deviation of 1VTH /VDSAT is 105 µV/91 mV.
Therefore, the calculated CMRR is 58.8 dB, which approxi-
mates the measurement result (52 dB). Although the measured
intrinsic CMRR is quite low, it is boosted to 86 dB by enabling
the driven-right-leg (DRL) circuit. The DRL circuit extracts
Fig. 19. Measured CMRR w/ and w/o DRL.
the common-mode voltage from the differential inputs. The
extracted common-mode voltage is subsequently amplified
through an inverting amplifier and fed back to the subject via
setup. We did the measurements as follows: Place the an extra DRL electrode. In this manner, the common-mode
Direct-FE into a Faraday cage (for better shielding from interference at the input is subtracted, thereby increasing the
interference) with a resistor R S in series with its input. Then equivalent CMRR. The CMRR could be improved by the
measure the end-to-end voltage gain of the Direct-FE with common-mode replication method [51] as well.
and without R S in series (G 1 and G 2 ), respectively. The input To validate the effectiveness of the proposed DEM, Fig. 20
impedance can be calculated from G 1 and G 2 . shows comparison of the output spectrum of the Direct-FE
Fig. 19 shows the measurement results of the CMRR. The with ON/OFF DEM. The SFDR and the SNDR are improved
measurement setup is similar to [11]. The intrinsic CMRR can approximately by 20 dB. The capacitance mismatch in the
be calculated as follows: C-DAC and the gain mismatch are modulated to 706 Hz,
corresponding to the period of completing the DEM operation
1 1
CMRR = 1Z L 1 1gm
≈ 1gm
(60 kHz/85 ≈ 706 Hz). This out-of-band harmonic with a fixed
Z L 2gm Z B +1
+ gm gm frequency can be eliminated in the back-end digital signal
1 processing. Fig. 20 shows the measured noise floor. The IRN
= (20)
1VTH
+ 1K ′
+ 1W/L (0.5–125 Hz) is calculated to be 2.2 µVrms . It is acceptable in
VDSAT K′ W/L
most of the wearable devices, considering that the background
where Z B and Z L are the impedance of the tail current and noise is on the order of 10 µVrms [33], [39].
the output load, respectively. VDSAT is the overdrive voltage, Fig. 21 shows the measured SNDR/SNR versus the input
VTH is the threshold voltage, K ′ equals to µ p Cox , and W/L amplitude. The peak SNDR is 102 dB, whereas the DR is
is the aspect ratio of the differential pairs. According to the 112 dB. It can be observed that SNDR drops slightly during
calculation, two main factors that affect the intrinsic CMRR the transition from SAR-ADC-only to two-step conversion.
are: 1) mismatch of gm between the two input pairs and When the input signal amplitude is less than 3/7 · VDD /A A
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12 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 22. Measured SNR and simulated SQNR versus gain error.

(approximately −46 dBFS), it is amplified through a fixed

gain A A (=85), while the Direct-FE works in SAR-ADC-only
mode. The first stage recovers to a conventional high-gain
amplifier for small amplitude input, as the C-DAC of 1M does
not respond in such cases. When the input signal amplitude
exceeds the threshold value, the coarse quantizer begins to
respond, resulting in a natural transition to the two-step
conversion mode. With a small amplitude input, the harmonic
distortion is mainly caused by the non-linear C-DAC in the
SAR-ADC. As the input amplitude increases, the harmonics
become dominated by 1M, which can be effectively reduced
using DEM. The DR is ultimately extended by approximately
50 dB compared with SAR-ADC-only conversion.
As previously discussed, the gain error arising from the
coarse ADC and the fine ADC leads to quantization noise leak-
age and thus SQNR degeneration. The accurate analog gain
(A A ) can be measured from the amplitude between the analog
input VIN and the reconstructed digital counterpart DOUT in
an FB manner. Specifically speaking, by tuning the digital Fig. 23. Real-life wearable bio-potential recording (ECG, EM, and EEG).
weight A D in a FB loop, we can obtain the condition when
the amplitude of DOUT equals the analog input. Then the gain
error between A A and A D can be measured correspondingly.
Based on the measured gain error, the change in SNR with gain
error can be measured by changing the weights for A D during
signal reconstruction. Fig. 22 shows the measured SNR and
the simulated SQNR as a function of the gain error. In the
proposed FB architecture, when the gain error is 1%, the
SNR decreases by only 1 dB. In comparison, the SQNR of
the FF architecture decreases by almost 20 dB with 1% gain
error. It could thus be concluded that the tolerance to gain
error is significantly improved in the proposed FB architecture.
In real applications, gain trimming can be additionally used to
compensate the gain error to ensure the best SNR. Since SNR
degradation caused by the gain drift is significantly reduced,
the calibrated SNR could be well-guaranteed within a wide
temperature range.
Fig. 23 exhibits the in vivo measurement results by placing
the ECG patch on the chest of the subject through clothing.
Fig. 24. Testing environment and the prototype.
Meanwhile, non-contact ECG can be successfully recorded
with MAs up to 340 mV induced by jogging (A1). The
conventional ECG-recording AFE uses the same gain (=85) in the non-contact static ECG measurement results as shown
with a 12-bit SAR-ADC, while its supply voltage is 5 V. in A2. The forehead eye movement (EM) and EEG have
In the presence of 340-mV large MAs, the conventional AFE been successfully recorded as well (B and C). Clear α waves
has been saturated. The Q − R − S complex is clearly visible can be observed when the eyes are closed. Fig. 24 exhibits

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HAO et al.: 26-G INPUT-IMPEDANCE 112-dB DYNAMIC-RANGE TWO-STEP DIRECT-CONVERSION FRONT-END 13

TABLE I
C OMPARISON W ITH OTHER S TATE - OF - THE -A RT W ORKS

is mainly attributed to the proposed two-step direct conversion

architecture. Although TI’s ADS1299 achieves higher DR
(125 dB) based on the conventional architecture (IA + ADC),
it consumes much more (80×) power, which might be a
concern for wearable devices, particularly for multi-channel
wearable bio-potential acquisition. Table I shows comparison
of this work with state-of-the-art bio-potential acquisition FEs.
The proposed Direct-FE presents an advanced DR/SNDR.
The experimental results demonstrate its capability for
artifact-tolerant wearable bio-potential acquisition.

V. C ONCLUSION
This article presents a novel high DR Direct-FE for wear-
able acquisition of weak bio-potential signals in the presence
of large MAs, effectively preventing signal saturation. Ben-
Fig. 25. Directed-FEs survey: DR versus FoMDR .
efiting from the proposed FB two-step direct conversion
architecture with an improved 1-modulation, as well as a
the testing environment and the prototype used in the in vivo novel DDA and a DEM technique, it exhibits remarkable
measurement. performance, including a peak input range of 3.56 VPP , a low
Fig. 25 shows comparison of the performance with other IRN of 2.2 µVrms , a high DR of 112 dB, a high input
state-of-the-art Direct-FEs. Benefiting from the proposed impedance of 26 G, and a ±1.8-V EDO tolerance, while
architecture and circuit implementation, this work achieves consuming only 63-µW power. Apart from applying to wear-
an advanced DR and a competitive FoMDR . To the best able bio-potential acquisition, the proposed approach could
knowledge of the author, it is the first reported Direct-FE be expanded as a key technology to other relevant applica-
with over 110-dB DR. The internal supply for the DDA’s tions that require high DR. For instance, in the closed-loop
input is increased from 1.8 to 3.0 V (by 4.5 dB), while the brain–computer interface (BCI), the residual charge resulting
dynamic range is improved by more than 20 dB compared from the stimulation current leads to artifacts up to several
with the state-of-the-art Direct-FE [22], [24], [31], [32]. This volts, which could be six orders of magnitude larger than the

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14 IEEE JOURNAL OF SOLID-STATE CIRCUITS

nerve signals [52], [53]. The proposed DR extension tech- [19] Y. Jung et al., “A wide-dynamic-range neural-recording IC with
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saturation-free closed-loop neural interfaces,” IEEE J. Solid-State Cir-
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acquisition together with large MAs, boosting the wearable [20] R. Rieger and Y.-Y. Pan, “A high-gain acquisition system with very large
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HAO et al.: 26-G INPUT-IMPEDANCE 112-dB DYNAMIC-RANGE TWO-STEP DIRECT-CONVERSION FRONT-END 15

[38] K. Jeong, S. Ha, and M. Je, “A 15.4-ENOB, fourth-order truncation- Hua Fan (Member, IEEE) received the B.S. degree
error-shaping NS-SAR-nested 16 modulator with boosted input in communications engineering and the M.S. degree
impedance and range for biosignal acquisition,” IEEE J. Solid-State in computer science and technology from Southwest
Circuits, vol. 59, no. 2, pp. 528–539, Feb. 2024. Jiaotong University, Chengdu, China, in 2003 and
[39] W. Wattanapanitch, M. Fee, and R. Sarpeshkar, “An energy-efficient 2006, respectively, and the Ph.D. degree from
micropower neural recording amplifier,” IEEE Trans. Biomed. Circuits Tsinghua University, Beijing, China, in July 2013.
Syst., vol. 1, no. 2, pp. 136–147, Jun. 2007. From September 2013 to June 2016, she was an
[40] H. Jeon, J.-S. Bang, Y. Jung, I. Choi, and M. Je, “A high DR, DC- Assistant Professor at the University of Electronic
coupled, time-based neural-recording IC with degeneration R-DAC for Science and Technology of China, Chengdu. From
bidirectional neural interface,” IEEE J. Solid-State Circuits, vol. 54, July 2016 to July 2021, she was an Associate
no. 10, pp. 2658–2670, Oct. 2019. Professor at the University of Electronic Science
[41] C. Lee et al., “A 6.5-µW 10-kHz BW 80.4-dB SNDR Gm -C-based CT and Technology of China. Since July 2021, she has been a Professor at the
16 modulator with a feedback-assisted Gm linearization for artifact- University of Electronic Science and Technology of China.
tolerant neural recording,” IEEE J. Solid-State Circuits, vol. 55, no. 11, Dr. Fan is the Associate Editor of IEEE T RANSACTIONS ON C IRCUITS AND
pp. 2889–2901, Nov. 2020. S YSTEMS —II: E XPRESS B RIEFS.
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based sensor front-end enabled by background-calibrated differential
pulse code modulation,” IEEE J. Solid-State Circuits, vol. 56, no. 4,
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[43] C. Pochet and D. A. Hall, “A 4.4 µW 2.5 kHz-BW 92.1dB-SNDR
3rd-order VCO-based ADC with pseudo virtual ground feedforward Yong Lian (Fellow, IEEE) research interests are in
linearization,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. the areas of self-powered smart wireless sensors,
Papers, Feb. 2022, pp. 408–410. energy-efficient event-driven signal processing tech-
[44] C. C. Lee and M. P. Flynn, “A SAR-assisted two-stage pipeline ADC,” niques, and biomedical circuits and systems.
IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 859–869, Apr. 2011. Mr. Lian is a fellow of the Canadian Academy
of Engineering and the Academy of Engineer-
[45] H. Alzaher and M. Ismail, “A CMOS fully balanced differential dif-
ing Singapore. He was a recipient of more than
ference amplifier and its applications,” IEEE Trans. Circuits Syst. II,
15 awards including the 2023 IEEE Circuits and
Analog Digit. Signal Process., vol. 48, no. 6, pp. 614–620, Jun. 2001.
Systems Society Mac Van Valkenburg Award,
[46] J. Jun, S. Park, J. Kang, and S. Kim, “A 22-bit read-out IC with 7-ppm
the 2023 IEEE Transactions on Biomedical Circuits
INL and sub-100-µHz 1/ f corner for DC measurement systems,” IEEE
and Systems Best Paper Award, the Design Contest
J. Solid-State Circuits, vol. 54, no. 11, pp. 3086–3096, Nov. 2019.
Award at 2015 International Symposium on Low Power Electronics and
[47] R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. H. Huijsing, Design, the 2011 Institution of Engineers Singapore Prestigious Engineering
“A compact power-efficient 3 V CMOS rail-to-rail input/output opera- Achievement Award, the 2008 IEEE Communications Society Multimedia
tional amplifier for VLSI cell libraries,” IEEE J. Solid-State Circuits, Communications Best Paper Award, and the 1996 IEEE Circuits and Systems
vol. 29, no. 12, pp. 1505–1513, Dec. 1994. Society Guillemin-Cauer Award. He serves as the IEEE Division 1 Director,
[48] D. Zhang, A. Bhide, and A. Alvandpour, “A 53-nW 9.1-ENOB 1-kS/s a member of the IEEE Board of Directors, the Member-at-Large of the IEEE
SAR ADC in 0.13-µm CMOS for medical implant devices,” IEEE J. Publication Services and Products Board, a member of the IEEE Technical
Solid-State Circuits, vol. 47, no. 7, pp. 1585–1593, Jul. 2012. Activities Board, the Chair for the IEEE Periodicals Partnership Opportunities
[49] A. Shabra, Y.-S. Shu, S.-H. Wen, and K.-D. Chen, “Design techniques Committee, the Chair of the IEEE Ad Hoc Committee on Accelerating
for high linearity and dynamic range digital to analog converters,” in Partnerships with Chinese Publications, a member of the IEEE Periodicals
Proc. IEEE Custom Integr. Circuits Conf. (CICC), Apr. 2022, pp. 1–8. Committee, a member of the IEEE Periodicals Review and Advisory Com-
[50] R. Adams and K. Q. Nguyen, “A 113-dB SNR oversampling DAC mittee, a member of the IEEE MGA Strategic Planning Committee, and a
with segmented noise-shaped scrambling,” IEEE J. Solid-State Circuits, member of the IEEE Fellow Committee. He was the President of the IEEE
vol. 33, no. 12, pp. 1871–1878, Dec. 1998. Circuits and Systems Society, the Editor-in-Chief of IEEE T RANSACTIONS
[51] S. Zhang, X. Zhou, C. Gao, and Q. Li, “A 130-dB CMRR instrumen- ON C IRCUITS AND S YSTEMS —II: E XPRESS B RIEFS , the Vice President for
tation amplifier with common-mode replication,” IEEE J. Solid-State Publications, the Vice President for Region 10 of the IEEE CAS Society, and
Circuits, vol. 57, no. 1, pp. 278–289, Jan. 2022. many other roles in IEEE. He is the founding Editor-in-Chief of the Journal
[52] S. Stanslaski et al., “Design and validation of a fully implantable, of Integrated Circuits and Systems.
chronic, closed-loop neuromodulation device with concurrent sensing
and stimulation,” IEEE Trans. Neural Syst. Rehabil. Eng., vol. 20, no. 4,
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[53] C.-W. Huang, C.-K. Lai, C.-C. Hung, C.-Y. Wu, and M.-D. Ker,
“A CMOS synchronized sample-and-hold artifact blanking analog front-
end local field potential acquisition unit with ±3.6-V stimulation artifact Mingyi Chen (Senior Member, IEEE) received the
tolerance and monopolar electrode-tissue impedance measurement cir- B.S. and M.S. degrees from Tianjin University,
cuit for closed-loop deep brain stimulation SoCs,” IEEE Trans. Circuits Tianjin, China, in 2004 and 2007, respectively, and
Syst. I, Reg. Papers, vol. 70, no. 6, pp. 2257–2270, Jun. 2023. the Ph.D. degree from the Chinese Academy of Sci-
[54] G. Kim et al., “A 1V-supply 1.85VPP -input-range 1kHz-BW ence, Beijing, China, in 2014, all in microelectronics
181.9dBFoMDR 179.4dB-FoMSNDR 2nd -order noise-shaping SAR-ADC and solid-state electronics.
with enhanced input impedance in 0.18 µm CMOS,” in IEEE Int. Solid- From 2007 to 2009, he worked as an Analog
State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2023, pp. 484–486. Designer at Trident Multimedia Technology Inc.,
Shanghai, China, designing high-performance low-
jitter PLLs. From 2009 to 2015, he worked as a
Principle Analog Designer at Smart-Chip Integra-
tion Inc., Suzhou, China, designing audio CODEC, wireless tuner, PLLs
and base-band ADCs for Wi-Fi/Bluetooth. From 2016 to 2018, he was
Yuzhi Hao was born in Nei Mongol, China,
a Post-Doctoral Research Fellow at IMEC, Leuven, Belgium, designing
in 1996. He received the B.S. degree in electronic
high-performance biomedical front-end for non-contact vital signal acqui-
science and technology from Tianjin University,
sition. In 2019, he joined Shanghai Jiao Tong University, Shanghai, where
Tianjin, China, in 2019. He is currently pursuing the
he is currently a Tenure-Track Associate Professor with the Department
Ph.D. degree with Shanghai Jiao Tong University,
of Micro/Nano Electronics, School of Electronic Information and Electrical
Shanghai, China.
Engineering. His research interests include designing analog/mixed-signal
His current research interests include
circuits, high-accuracy signal conditioning chain, sensor/biomedical interface,
high-performance analog front-end and direct
energy harvesting, and power management unit.
conversion front-end IC design.
Dr. Chen won the seal of excellence under 2018’s Marie Skłodowska-Curie
actions.

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