WORK IS WORSHIP

Digital VLSI Design – S6ECI01

Raveesh S.
Assistant Professor
Department of Electronics and Communication Engineering
Siddaganga Institute of Technology
Tumakuru – 572 103

Slides adopted from

1. Neil H.E. Weste, David Harris, Ayan Banerjee, CMOS VLSI Design, Pearson Education, 3rd Edition, 2006
2. Introduction to VLSI Circuits and Systems - John P Uyemura, John Wiley 2002
3. Sung MO Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits, Tata McGraw Hill, 3rd Edition, 2003.
Unit -2 CMOS Processing Technology
• Introduction,
• CMOS Technologies
– Wafer Formation
– Photolithography
– Well and Channel Formation
– Silicon Dioxide
– Isolation, Gate Oxide
– Gate and Source/Drain Formations
– Contacts and Metallization
– Passivation, Metrology
• Layout Design Rules
– Well rules
– Transistor rules
– Contact rules
– metal rules
– via rules
– other rules
Fabrication
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• [Link]
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CMOS technologies
• Simplified treatment of the process steps
– n-well process
– p-well process
– twin-well process
– triple-well process
Wafer formation
• Czochralski technique (CZ)
• Float zone technique

• Czochralski technique (CZ)

• furnace is heated above 1500 0C
• A seed crystal of desired
orientation is inserted
• Currently varies from 50-450mm
• Growth rate 30 to 180mm /hour
• Atmosphere He or Argon
• 9N purity

[Link]
Silicon dioxide
• Silicon has dominated the industry because it
has an easily processable oxide
• Thin oxides are required for transistor gates;
thicker oxides might be required for higher
voltage devices
• Oxidation of silicon is achieved by heating
silicon wafers in an oxidizing atmosphere

[Link]
Silicon dioxide (contd.)
• Wet oxidation
– Oxidizing atmosphere contains water vapor.
– Temperature between 900 °C and 1000 °C.
– This is also called pyrogenic oxidation, a 2:1 mixture of
hydrogen and oxygen is used.
– Wet oxidation is a rapid process.
• Dry oxidation
– Oxidizing atmosphere is pure oxygen.
– Temperatures are in the region of 1200 °C to achieve an
acceptable growth rate.
– Dry oxidation forms a better quality oxide than wet oxidation.
– It is used to form thin, highly controlled gate oxides, while wet
oxidation may be used to form thick field oxides.
• Atomic layer deposition (ALD)
– when a thin chemical layer (material A) is attached to a surface
and then a chemical (material B) is introduced to produce a
thin layer of the required layer
Photolithography
• Greek photo (light), lithos (stone), and graphe
(picture), means “carving pictures in stone using
light.”
• The wafer is coated with the photoresist and
subjected to selective illumination through the
photomask
• A photomask is constructed with chromium
(chrome) covered quartz glass
• A UV light source is used to expose the
photoresist
Photolithography (contd.)

Photo-mask

Photoresist (PR)

Substrate

Positive PR Negative PR

Unexposed area Exposed area

After the development
Photolithography (contd.) exposure technique

Light source

Photo-mask
Photoresist (PR)

Substrate

Contact Proximity Projection

printing printing printing
Photolithography (contd.)
• Photo masking with a negative resist
Challenges in lithography

IDE

[Link]
Photolithography (contd.)
• Positive photoresist
• Negative photoresist
• The photomask is commonly called a reticle and
is usually smaller than the wafer
• A stepper moves the reticle to successive
locations to completely expose the wafer
– Projection printing
– Contact printing
– Proximity printing
Photolithography (contd.)
• Minimum pitch (width + spacing) of a process to be 2b
• The resolution of a lens depends on the wavelength λ of
the light and the numerical aperture NA of the lens

n is the refractive index of the medium (1 for air,

1.33 for water, and up to 1.5 for oil), and αis the
angle of acceptance of the lens
Photolithography (contd.)
• In the 1980s, mercury lamps with 436 nm or 365
nm wavelengths were used
• At the 0.25 μm process generation, excimer lasers
with 248 nm (deep ultraviolet) were adopted and
have been used down to the 180 nm node.
• 193 nm argon-fluoride lasers are used for the
critical layers down to the 45 nm node and beyond
• Efforts to develop 157 nm deep UV lithography
systems were unsuccessful and have been
abandoned by the industry
N-well process
• Blank wafer covered with a layer of SiO2 using oxidation

• Spin on the photoresist. Exposed to UV light using the n-well

mask. (Photolithography)

• Strip off the exposed photoresist using organic solvents

N-well process (contd.)
• Etch the uncovered oxide using HF (Hydroflouric acid)

• Etch the remaining photoresist using a mixture of acids

• n-well is formed using either diffusion or ion implantation

N-well process (contd.)
• Strip off remaining oxide using HF. Subsequent steps use the
same photolithography process

• Deposit thin layer of oxide. Use CVD to form poly and dope
heavily to increase conductivity

• Pattern poly using the previously discussed photolithography

process
N-well process (contd.)
• Cover with oxide to define n diffusion regions

• Pattern oxide using n+ active mask to define n diffusion regions

• Diffusion or ion implantation used to create n diffusion regions

N-well process (contd.)
• Strip off the oxide to complete patterning step

• Similar steps used to create p diffusion regions

• Cover chip with thick field oxide and etch oxide where contact
cuts are needed
N-well process (contd.)
• Remove excess metal leaving wires

• Layout (mask) view of the inverter

N –well masks
• Six masks
– n-well
– Polysilicon
– n+ diffusion
– p+ diffusion
– Contact
– Metal
p-well process

• The fabrication of p-well CMOS process is

similar to n-well process except that p-wells
acts as substrate for the n-devices within the
parent n- substrate
Advantages of n-well process
• n-well CMOS are superior to p-well because of
lower substrate bias effects on transistor
threshold voltage
• lower parasitic capacitances associated with
source and drain region
• Latch-up problems can be considerably reduced
by using a low resistivity epitaxial p-type
substrate
Twin tub process

[Link]
Triple-well process

[Link]
m/pdfs/aa697f72676b4bc4426b/[Link]
Isolation
• Individual devices in a
CMOS process need to be
isolated
• Transistor gate consists of
a thin gate oxide layer.
Elsewhere, a thicker layer
of field oxide separates
polysilicon and metal
wires from substrate
• Thick oxide effectively
sets a threshold voltage
greater than VDD [Link]
• Local Oxidation of Silicon [Link]
(LOCOS)
• laterally extension so-
called bird’s beak
IC Fabrication

• [Link]
• [Link]

• [Link]
• [Link]
Isolation (contd.)
• 0.5/0.35 μm node on wards shallow trench
isolation (STI)
• Avoids the bird's beak
• STI starts with a pad oxide and a silicon nitride
layer, which act as the masking layers,
• Openings in the pad oxide are then used to etch
into the well or substrate region
• A liner oxide is then grown to cover the exposed
silicon
Isolation (contd.)
• The trenches are filled with SiO2 or other fillers
using CVD that does not consume the underlying
silicon
• The pad oxide and nitride are removed and a
Chemical Mechanical Polishing (CMP) step is used to
planarize the structure
• Mechanical grinding action in which the rotating
wafer is contacted by a stationary polishing head
while an abrasive mixture is applied
Gate oxide
• Gate oxide for the transistors
• The oxide structure is called the gate stack
• A pure SiO2 gate oxide - stack that consists of a few
atomic layers, each 3–4 A thick
• Many processes in the 180 nm generation and
beyond provide at least two oxide thicknesses
• Thin for logic transistors and thick for I/O
transistors that must withstand higher voltages
Gate and Source/Drain formations
• When silicon is deposited on SiO2 or other surfaces
without crystal orientation - polycrystalline silicon
commonly called polysilicon
• Undoped polysilicon has high resistivity
• The resistance can be reduced by implanting it
with dopants and/or combining it with a
refractory metal
• The polysilicon gate serves as a mask to allow
precise alignment of the source and drain on either
side of the gate
• Self-aligned polysilicon gate process
Gate and Source/Drain formations (contd.)
• first diffused
source and drain
regions, and then
formed a metal
gate – misaligned
– fail
• overhang the
source and drain
by more than the
alignment
tolerance – large
parasitic
[Link]
Gate and Source/Drain formations (contd.)
• Self-aligned Process
– Grow gate oxide wherever transistors are required (area =
source + drain + gate)

– Deposit polysilicon on chip

Gate and Source/Drain formations (contd.)

– Pattern polysilicon (both

gates and interconnect)

– Etch exposed gate oxide

– Implant pMOS and nMOS

source/drain regions
Gate and Source/Drain formations (contd.)
• The n-pockets (LDD) doped to medium conc are used to
smear out the strong E-field between the channel and heavily
doped n+ S/D, in order to reduce hot-carrier generation - and
suppresses shortchannel effects
• LDD structures exhibit low capacitance but high resistance
• heavily doped source/ drain implants are needed in
conjunction with the LDD implants
• silicon nitride spacer along the edge of the gate serves as a
mask to define the deeper diffusion regions
Contacts and metallization
• Contact cuts are made
to source, drain, and
gate according to the
contact mask
• These are holes etched
in the dielectric after
the source/drain step
• Metallization is the
process of building
wires to connect the
devices
• evaporation or
sputtering
• Wet or dry etching
Passivation
• protective
glass layer
called
passivation or
overglass that
prevents the
ingress of
contaminants

[Link]
Metrology
• Science of measuring
• Feedback to the manufacturing process
• Optical microscopes
• Scanning electron microscopy (SEM)
• Energy Dispersive Spectroscopy (EDX)
• Transmission Electron Microscope (TEM)
 End of
Unit-2, Part-1