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The document is a descriptive test paper for II B.Tech I Semester students in the ECE department at KKR & KSR Institute of Technology and Sciences. It includes various questions related to digital circuits, such as constructing a full adder, comparing memory types, and explaining flip-flops and counters. The test is designed to assess students' understanding of sequential circuits and state machine conversions.

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chinnarrr
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17 views1 page

Mid2 Format

The document is a descriptive test paper for II B.Tech I Semester students in the ECE department at KKR & KSR Institute of Technology and Sciences. It includes various questions related to digital circuits, such as constructing a full adder, comparing memory types, and explaining flip-flops and counters. The test is designed to assess students' understanding of sequential circuits and state machine conversions.

Uploaded by

chinnarrr
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

KKR & KSR INSTITUTE OF TECHNOLOGY AND SCIENCES

(Approved by AICTE, New Delhi, Affiliated to JNTU Kakinada)


Department: ECE Date: 11-10-2019
Class: II [Link] I Sem Academic Year: 2019-20
Descriptive Test No: 02 Branch: ECE Sub: STLD
Name: Max. Time: 90 Min
Regd No: Max. Marks: 30
ANSWER ALL OF THE FOLLOWING
[Link] Question Marks CO LL
a) Construct and implement full adder with PLA 5 C202.4 L3
1
b) Give the comparison between PROM, PLA and PAL. 5 C202.4 L3
a) Build the JK flip flop using AND gates and NOR gates. Explain C202.5
the operation of the JK flip flop with the help of characteristic table 5 L3
2 and characteristic equation. Convert T flip flop into JK flip flop.
b) Construct mod-12 counter using NAND gates and JK flip flops. C202.5
5 L3
Design 3bit Ring counter.
a) Explain about sequential circuits, state table and state diagram, C202.6
5 L2
3 state assignment, state reduction.
b) Explain the procedure of melay to moore conversion. 5 C202.6 L2

KKR & KSR INSTITUTE OF TECHNOLOGY AND SCIENCES


(Approved by AICTE, New Delhi, Affiliated to JNTU Kakinada)
Department: ECE Date: 11-10-2019
Class: II [Link] I Sem Academic Year: 2019-20
Descriptive Test No: 02 Branch: ECE Sub: STLD
Name: Max. Time: 90 Min
Regd No: Max. Marks: 30
ANSWER ALL OF THE FOLLOWING

[Link] Question Marks CO LL


a) Construct and implement full adder with PLA 5 C202.4 L3
1
b) Give the comparison between PROM, PLA and PAL. 5 C202.4 L3
a) Build the JK flip flop using AND gates and NOR gates. Explain C202.5
the operation of the JK flip flop with the help of characteristic table 5 L3
2 and characteristic equation. Convert T flip flop into JK flip flop.
b) Construct mod-12 counter using NAND gates and JK flip flops. C202.5
5 L3
Design 3bit Ring counter.
a) Explain about sequential circuits, state table and state diagram, C202.6
5 L2
3 state assignment, state reduction.
b) Explain the procedure of melay to moore conversion. 5 C202.6 L2

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