Timing Diagram
The 8085 instructions consist of one to five machine cycles.
Actually the execution of an instruction is the execution of the machine cycles of
that instruction in the predefined order.
The timing diagram of an instruction ate obtained by drawing the timing diagrams
of the machine cycles of that instruction, one by one in the order of execution.
Representation of Various Control signals generated during Execution of an Instruction.
Following Buses and Control Signals must be shown in a Timing Diagram:
• Higher Order Address Bus.
• Lower Address/Data bus
• ALE
• RD
• WR
• IO/M
Opcode fetch machine cycle of 8085 :
Each instruction of the processor has one byte opcode.
The opcodes are stored in memory. So, the processor executes the opcode fetch
machine cycle to fetch the opcode from memory.
Hence, every instruction starts with opcode fetch machine cycle.
The time taken by the processor to execute the opcode fetch cycle is 4T.
In this time, the first, 3 T-states are used for fetching the opcode from memory
and the remaining T-states are used for internal operations by the processor.
1
Memory Read Machine Cycle of 8085:
The memory read machine cycle is executed by the processor to read a data byte
from memory.
The processor takes 3T states to execute this cycle.
The instructions which have more than one byte word size will use the machine cycle
after the opcode fetch machine cycle.
2
Memory Write Machine Cycle of 8085:
The memory write machine cycle is executed by the processor to write a data byte
in a memory location.
The processor takes, 3T states to execute this machine cycle.
3
I/O Read Cycle of 8085:
The I/O Read cycle is executed by the processor to read a data byte from I/O port
or from the peripheral, which is I/O, mapped in the system.
The processor takes 3T states to execute this machine cycle.
The IN instruction uses this machine cycle during the execution.
4
I/O Write Cycle of 8085:
The I/O write machine cycle is executed by the processor to write a data byte in
the I/O port or to a peripheral, which is I/O, mapped in the system.
The processor takes, 3T states to execute this machine cycle.
5
Timing Diagram
Instruction: T1 T2 T3 T4
A000h MOV A,B A0h
A15- A8 (Hi gher Order Address bus)
Corresponding Coding: 00h 78h
A000h 78
ALE
RD
OFC WR
IO /M
8085 Memory
Op-code fetch Cycle
6
7
Timing Diagram
Instruction:
A000h LXI H, FO45h
Corresponding Coding:
A000h 21
A001h 45
A002h F0
8
Timing diagram for INR M
Fetching the Opcode 34H from the memory 4105H. (OF cycle)
Let the memory address (M) be 4250H. (MR cycle -To read Memory address and
data)
Let the content of that memory is 12H.
Increment the memory content from 12H to 13H. (MW machine cycle)
9
Timing diagram for MVI B, 43H.
Fetching the Opcode 06H from the memory 2000H. (OF machine cycle)
Read (move) the data 43H from memory 2001H. (memory read)
10
+
Timing diagram for STA 526AH.
STA means Store Accumulator -The contents of the accumulator is stored in the
specified address(526A).
The opcode of the STA instruction is said to be 32H. It is fetched from the
memory 41FFH(see fig). - OF machine cycle
11
Then the lower order memory address is read(6A). - Memory Read Machine
Cycle
Read the higher order memory address (52).- Memory Read Machine Cycle
The combination of both the addresses are considered and the content from
accumulator is written in 526A. - Memory Write Machine Cycle
Assume the memory address for the instruction and let the content of accumulator
is C7H. So, C7H from accumulator is now stored in 526A.
Timing diagram for IN C0H.
Fetching the Opcode DBH from the memory 4125H.
Read the port address C0H from 4126H.
Read the content of port C0H and send it to the accumulator.
12
Let the content of port is 5EH.
13
