Indian Institute of Technology Delhi

Department of Electrical Engineering

ELL201 - Digital Electronics

Laboratory
Lab Report 6
Experiment: Verilog Simulations - Counters

Experiment Started: 11th April 2025

Experiment Completed: 11th April 2025
Submission Date: 21st April 2025
Table No.: 17 (Friday Batch)

Submitted By:
Anurag Agarwal 2023MT10312

Vanshika Bathla 2023EE30828

Aditya Gupta 2023EE11181

Vishnu Kumawat 2023EE30758

Under the Guidance of the TA:

Mr. Rupesh Kumar
Academic Session: 2024–2025 (Semester
II) IIT Delhi
Lab 6: Verilog Simulations - ELL201 Lab

Contents

1 Aim 2

2 Apparatus and Tools 2

3 Theory 2
3.1 Gray Code Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
3.2 SR Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.3 Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
3.4 D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Design and Implementation 3

4.1 Gray Code Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
4.1.1 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
4.1.2 Flip-Flop Inputs and K-Maps . . . . . . . . . . . . . . . . . . . .3
4.1.3 Boolean Expressions . . . . . . . . . . . . . . . . . . . . . . . . .5
4.1.4 Verilog Code for SR FF and Counter . . . . . . . . . . . . . . . .5
4.1.5 Simulation and Output . . . . . . . . . . . . . . . . . . . . . . . .7
4.2 Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.2.1 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.2.2 Initial State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.3 State and D Flip-Flop Table . . . . . . . . . . . . . . . . . . . . .8
4.2.4 Verilog Code for D FF and Counter . . . . . . . . . . . . . . . . .9
4.2.5 Simulation and Output 10

5 Observations 12

6 Inference 12

7 Conclusion 12

8 Sources of Error 12

9 Precautions 13

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Lab 6: Verilog Simulations - ELL201 Lab

1 Aim
To design and simulate two types of synchronous counters using Verilog:

• A 4-bit Gray Code Counter using SR Flip-Flops

• A Synchronous Ring Counter using D Flip-Flops

2 Apparatus and Tools

1. Verilog Simulator (ModelSim, GTKWave)

2. Digital Design Tools (for K-Maps)

3. SR and D Flip-Flop Modules

3 Theory

3.1 Gray Code Counter

A Gray Code counter changes only one bit between consecutive states, reducing
errors due to glitches during transitions. This is crucial in high-speed applications
like rotary encoders and ADC circuits, where stability is essential.
Also known as reflected binary code, it is widely used in systems that require
error-free transitions, such as counters, memory addressing, and position
encoders.

3.2 SR Flip-Flop
The SR (Set-Reset) flip-flop is a fundamental bistable element with inputs S and
R, and outputs Q and Q’. It retains its output until either input is triggered —
setting Q to 1 or resetting it to 0.
Used primarily in synchronous sequential logic, it serves as the memory element
in counters like the Gray Code counter, updating states based on input logic.

3.3 Ring Counter

A Ring Counter is a type of shift register where a bit pattern circulates through
flip- flops. In a 4-bit ring counter, a ‘1’ moves through each stage cyclically,

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Lab 6: Verilog Simulations - ELL201 Lab

repeating after a fixed number of clock cycles.

A Johnson Counter is a variant where feedback is applied differently, allowing
more states. These counters are common in timing and pattern generation
applications due to their simple, predictable behavior.

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Lab 6: Verilog Simulations - ELL201 Lab

3.4 D Flip-Flop
The D flip-flop captures input D on the edge of the clock and holds it at the
output Q. It is the most commonly used flip-flop in digital systems for data
storage, shift registers, and counters.
In a synchronous ring counter, D flip-flops shift states in a controlled manner,
enabling clean, edge-triggered transitions. Their reliable behavior makes them
ideal for sequential circuit design.

4 Design and Implementation

4.1 Gray Code Counter

4.1.1 Procedure

1. Begin by defining a 4-bit Gray code sequence that covers all 16 states in a
cyclic manner. Ensure only one bit changes between consecutive states.

2. As each bit of the counter’s state needs to be stored, determine that four
SR flip- flops are required—one for each bit.

3. For each transition in the Gray code sequence, assign the appropriate
Set (S) and Reset (R) inputs for each SR flip-flop to transition from the
current to the next state.

4. For every flip-flop, use Karnaugh Maps to minimize the Boolean expressions
for the S and R inputs as functions of the current output states.

5. Create a Verilog module for the SR flip-flop. Use these as components in

the main counter module.

6. Instantiate four SR flip-flops in the top-level counter module. Use the minimized
expressions from the K-maps to generate S and R inputs.

7. Make sure the SR flip-flops are implemented as positive- or negative-edge

triggered flip-flops (not latches), to ensure synchronous operation.

8. Simulate the counter using a Verilog simulator (like ModelSim or

GTKWave) and verify that the counter cycles through all 16 Gray code
states correctly.

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4.1.2 Flip-Flop Inputs and K-Maps

(SR Flip-Flop synthesis table and K-maps for S3-R3 to S0-

R0) No of states = 16 (4-bit counter)
Hence number of flip-flops used = log2 16 = 4

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Lab 6: Verilog Simulations - ELL201 Lab

Synthesis table using SR flip-flop:

Current State Next State Flip Flop 3 Flip Flop 2 Flip Flop 1 Flip Flop 0
Q3 Q2 Q1 Q0 Q3∗ Q2∗ Q1∗ Q0∗ S3 R3 S2 R2 S1 R1 S0 R0
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 0
0 0 1 0 0 1 1 0 X 0 X 1 0 X 0 1
0 0 1 1 0 0 1 0 X 0 X 0 0 X 1 0
0 1 0 0 1 0 0 0 X 1 0 X 0 X 0 X
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 0
0 1 1 1 0 1 0 0 X 1 0 X 0 X 0 X
0 1 0 1 1 0 0 1 1 0 X 0 0 X 0 1
1 0 0 1 1 1 0 0 X 0 0 X X 0 1 0
1 1 0 0 0 1 0 1 X 0 X 0 0 X 0 1
1 0 1 0 1 1 1 0 0 X 0 X X 0 1 0
1 1 1 0 0 1 1 1 0 X 0 X X 0 0 1
1 1 1 1 0 1 0 0 0 X 0 X 0 1 X 0
0 1 0 0 1 0 1 0 X 0 X 1 0 X 0 1
1 0 1 0 1 1 0 1 0 X 0 X 0 1 X 0
1 1 0 1 0 0 0 1 1 0 X 0 0 X 0 1
1 0 0 0 0 0 0 1 0 X 0 X 0 X 1 0

K-maps for flip-flop inputs:

K-map for S3/R3
Q1Q0
Q3Q2 00 01 11 10
00 0/X 0/X 0/X 0/X
01 1/0 0/X 0/X 0/X
11 X/0 X/0 X/0 X/0
10 0/1 X/0 X/0 X/0

K-map for S2/R2

Q1Q0
Q3Q2 00 01 11 10
00 0/X 0/X 0/X 1/0
01 X/0 X/0 X/0 X/0
11 X/0 X/0 X/0 0/1
10 0/X 0/X 0/X 0/X

K-map for S1/R1

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 Lab 6: Verilog Simulations - ELL201 Lab

Q1Q0
Q3Q2 00 01 11 10
00 0/X 1/0 X/0 X/0
01 0/X 0/X 0/1 X/0
11 0/X 1/0 X/0 X/0
10 0/X 0/X 0/1 X/0

K-map for S0/R0

Q1Q0
Q3Q2 00 01 11 10
00 1/0 X/0 0/1 0/X
01 0/X 0/1 X/0 1/0
11 1/0 X/0 0/1 0/X
10 0/X 0/1 X/0 1/0

4.1.3 Boolean Expressions

(Simplified expressions from K-maps)

S3 = Q2Q′ Q′
1 0
R3 = Q′ Q1Q′
2 0

S2 = Q3′ Q1Q0
R2 = Q3Q1Q
0 ′

S1 = Q3 ′ Q2Q0 + Q3Q2Q0
R1 = Q′ Q2Q0 + Q3Q′ Q0
3 2
S0 = Q′ Q′ Q′ + Q′ Q2Q1 + Q3Q′ Q1 + Q3Q2Q′
3 2 1 3 2 1
R 0 = Q ′ Q2Q1 + Q′ Q′ Q′ + Q3 + Q3Q2Q1
Q Q
′ ′
3 3 2 1 2 1

4.1.4 Verilog Code for SR FF and Counter

SR flip-flop implementation is positive edge triggered.

1 module srFF(clk,s,r,q);

2
input clk,s,r;
output q;
3
reg q;
4

always @(posedge clk) 9

 Lab 6: Verilog Simulations - ELL201 Lab

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8 if(s==1)
9 q = 1;

10
else if (r==1)

11
q = 0;
else if (s==0 & r==0)
12
q <= q;
13
end
14

15

Listing 1: SR Flip-Flop Implementation

4 flip-flops are used with 3,2,1,0 in decreasing order of significance.

1 module grayCounter;

2
reg s3,s2,s1,s0,r3,r2,r1,r0;
wire [3:0] q;
3
reg clk;
4

5
srFF ff3(clk,s3,r3,q[3]);
6
srFF ff2(clk,s2,r2,q[2]);
7 srFF ff1(clk,s1,r1,q[1]);
8 srFF ff0(clk,s0,r0,q[0]);
9

10
always @(negedge clk) begin
s3 = q[2] & ˜q[1] & ˜q[0];
11
r3 = ˜q[2] & ˜q[1] & ˜q[0];
12
s2 = ˜q[3] & q[1] & ˜q[0];
13
r2 = q[3] & q[1] & ˜q[0];
14
s1 = (˜q[3] & ˜q[2] & q[0])|(q[3] & q[2] & q[0]);
15
r1 = (˜q[3] & q[2] & q[0])|(q[3] & ˜q[2] & q[0]);
16 s0 = (˜q[3] & ˜q[2] & ˜q[1])|(˜q[3] & q[2] & q[1])|
17 (q[3] & ˜q[2] & q[1])|(q[3] & q[2] & ˜q[1]);
18 r0 = (˜q[3] & ˜q[2] & q[1])|(˜q[3] & q[2] & ˜q[1])|

19
(q[3] & ˜q[2] & ˜q[1])|(q[3] & q[2] & q[1]);
end
20

21
initial begin
22
$dumpfile("grayCounter.vcd");
23
$dumpvars(0,grayCounter);
24 $monitor($time," %b %b %b %b ",q[3],q[2],q[1],q[0]); s3
25 = 0; s2 = 0; s1 = 0; s0 = 0;
26 r3 = 1; r2 = 1; r1 = 1; r0 = 1;

27
clk = 1;
#66;
$finish;
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 Lab 6: Verilog Simulations - ELL201 Lab

28

29

30

31

32

33

34

35

36

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Lab 6: Verilog Simulations - ELL201 Lab

Listing 2: Gray Counter with 4 Flip-Flops

4.1.5 Simulation and Output

(Waveform image and timing table)

Figure 1: GTKWave [clk, q[3:0] vs time]

Figure 2: Output [Time Q3 Q2 Q1

Q0]

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Lab 6: Verilog Simulations - ELL201 Lab

Figure 3: Signed Copy by TA Figure 4: Signed Copy by TA

4.2 Ring Counter

4.2.1 Procedure

1. Determine the number of D flip-flops required based on the bit-width of the

counter (typically 4).

2. Refer to the state table to assign D input values for each flip-flop. For intermediate
flip-flops, the input is typically the output of the preceding flip-flop.

3. Handle the MSB input carefully, as it may be a combination of current outputs to

form a loop (e.g., for Johnson counters).

4. Choose the initial state as the 4-bit binary representation of the last digit of your
entry number (X4).

5. Write Verilog code for an edge-triggered D flip-flop module (not a latch), and use
these modules in the counter design.

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Lab 6: Verilog Simulations - ELL201 Lab

6. Connect the D inputs as per the logic derived from the state table and implement
the synchronous behavior.

7. Simulate the design and verify whether the counter reaches all 16 states or a
subset, depending on the initial state.
4.2.2 Initial State

Taking the last digit of the entry number as 8, whose 4 bit binary representation
is 1000, the initial state is initialized likewise.

4.2.3 State and D Flip-Flop Table

(State transition table and K-maps for D3-D0)

The counter has 4 bits; thus, the number of D flip-flops required is 4.

Synthesis Table (State Table):

Q3 Q2 Q1 Q0 D3 D2 D1 D0
0 0 0 1 1 0 0 0
1 0 0 0 0 1 0 0
0 1 0 0 0 0 1 0
0 0 1 0 1 0 0 1
1 0 0 1 1 1 0 0
1 1 0 0 0 1 1 0
0 1 1 0 1 0 1 1
1 0 1 1 0 1 0 1
0 1 0 1 1 0 1 0
1 0 1 0 1 1 0 1
1 1 0 1 0 0 1 1
1 1 1 0 1 0 1 1
0 1 1 1 1 1 1 1
1 1 1 1 0 0 0 1

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K-maps:

K-map for D3 K-map for D2

Q3Q2 \Q1Q0 00 01 11 10 Q3Q2 \Q1Q0 00 01 11 10
00 X 1 0 1 00 X 0 0 0
01 0 1 0 1 01 0 0 0 0
11 0 1 0 1 11 1 1 1 1
10 0 1 0 1 10 1 1 1 1
K-map for D1 K-map for D0
Q3Q2 \Q1Q0 00 01 11 10 Q3Q2 \Q1Q0 00 01 11 10
00 X 0 0 0 00 X 0 1 1
01 X 1 1 1 01 0 0 1 1
11 1 1 1 1 11 0 0 1 1
10 0 0 0 0 10 0 0 1 1

Simplified Boolean Expressions:

D3 = Q1 ⊕ Q0
D2 = Q
3 D1 =
Q2 D0
= Q1

4.2.4 Verilog Code for D FF and Counter

D Flip-Flop D flip-flop implementation is positive edge triggered.

1 module dFF(clk, d, q);

2
input clk, d; output
q;
3
reg q;
4

5
always @(posedge clk) begin
6
q = d;
7
end
8

Listing 3: Positive Edge Triggered D Flip-Flop

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 Lab 6: Verilog Simulations - ELL201 Lab

Ring Counter We require 4 ring counters with 3, 2, 1, 0 in decreasing order of

signif- icance.
module ringCounter;
1

2
reg clk;
3

4 reg d3, d2, d1, d0;

5 wire [3:0] q;
6

7 dFF dff3(clk, d3, q[3]);

8 dFF dff2(clk, d2, q[2]);
9 dFF dff1(clk, d1, q[1]);
10 dFF dff0(clk, d0, q[0]);
11

12 always @(negedge clk) begin

13 d3 = q[1] ˆ q[0];
14 d2 = q[3];
15 d1 = q[2];
16 d0 = q[1];
17 end
18

19 initial begin
20 $dumpfile("ringCounter.vcd");
21 $dumpvars(0, ringCounter);
22 $monitor($time, " %b %b %b %b ", q[3], q[2], q[1], q[0]);
23

24 d3 = 1;
25 d2 = 0;
26 d1 = 0;
27 d0 = 0;
28 clk = 1;
29 #66;
30 $finish;
31 end
32

33 always #2 clk = ˜clk;

34

35
endmodule

Listing 4: 4-bit Synchronous Ring Counter

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5 Observations
In the simulation of the 4-bit Gray Code Counter, the waveform demonstrated
that only one bit changed between any two consecutive states, confirming the
correct Gray code behavior. The counter successfully cycled through all 16
states in a loop without glitches, validating the logic. For the Ring Counter, the
waveform showed the cyclic shift of a ’1’ bit across the flip-flops, with the pattern
restarting after a fixed number of clock cycles. The transition patterns observed
in both counters aligned with their respective truth tables and design
expectations.

6 Inference
Both the Gray Code and Ring Counters exhibited synchronous operation, as
evidenced by the simultaneous triggering of all flip-flops on the clock edge. The
Gray Code Counter ensured minimal transitional errors by changing only one bit
at a time, while the Ring Counter followed a predictable loop based on the initial
state. The use of Karnaugh Maps for logic minimization and edge-triggered flip-
flops ensured clean, reliable state transitions.

7 Conclusion
This experiment demonstrated the successful design and simulation of two
synchronous counters using Verilog: a 4-bit Gray Code Counter and a
Synchronous Ring Counter. The Gray Code Counter, built with SR flip-flops, and
the Ring Counter, using D flip- flops, were both designed using logic derived
from state tables and K-maps. Simulations confirmed the correct behavior of both
counters, reinforcing concepts like sequential logic, edge-triggering, and state
transitions.
For the Ring Counter, only 15 states were observed (does not cover all 16
states), with the state 0000 missing. If initialized to 0000, all flip-flops remain at
0, resulting in no meaningful output. This highlights the pseudo-random nature of
the design, which produces a predictable sequence based on the initial state. In
our case, the sequence followed a pattern such as: 8 → 4 → 2 → 12 → 6 → 11 → 5
→ 10 → 13 → 14 → 15 →
7 → 3 → 1.
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Lab 6: Verilog Simulations - ELL201 Lab

8 Sources of Error
During the execution and simulation of the synchronous counters, the following
potential errors were identified:

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Lab 6: Verilog Simulations - ELL201 Lab

• Incorrect K-map Simplification: Errors while simplifying logic expressions us- ing
Karnaugh Maps could lead to faulty or unintended logic driving the flip-
flops.

• Clock Sensitivity Issues: Failing to define the flip-flops as edge-triggered (pos

- itive or negative edge) may result in latch behavior, leading to
asynchronous and unpredictable state changes.

• Verilog Syntax and Instantiation Errors: Mistakes such as incorrect module

instantiations, undeclared wires, or improper sensitivity lists can prevent
successful simulation or produce unexpected behavior.

• Uninitialized Flip-Flops: If the initial state of flip-flops is not correctly defined,

especially in ring counters, the circuit may enter invalid or stagnant states.

• Incorrect State Table Mapping: Mapping between current and next states may
be flawed if not properly cross-verified with the intended counter sequence.

9 Precautions
To ensure correct design, simulation, and analysis of the counters, the following
precau- tions should be taken:

• Use Edge-Triggered Flip-Flops: Always implement flip-flops with proper edge

sensitivity to maintain synchronous behavior and avoid unintended latch-
based transitions.

• Correct Initialization: Clearly define the initial state of all flip-flops, particularly
for ring counters, to ensure a predictable start to the sequence.

• Validate K-map Logic: Cross-verify the minimized expressions obtained

through Karnaugh Maps with the truth table or simulation results.

• Incremental Testing: Simulate individual modules like the flip-flops and test-
bench separately before integrating into the complete design.

• Verify Connections: Ensure that all modules are properly instantiated and
sig- nals are correctly wired, especially in hierarchical Verilog designs.

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Lab 6: Verilog Simulations - ELL201 Lab

• Waveform Analysis: Regularly analyze simulation waveforms to detect

glitches, undefined states, or timing mismatches during transitions.