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Digital Systems Design Lecture Notes Coen313

The document provides an overview of Finite State Machines (FSMs), including their representation, timing, and performance, as well as the differences between Moore and Mealy machines. It discusses the use of state diagrams and ASM charts for FSM design, and highlights VHDL descriptions and state assignment techniques. Additionally, it compares the advantages and disadvantages of Moore and Mealy machines in various applications.

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Asma Khider
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95 views28 pages

Digital Systems Design Lecture Notes Coen313

The document provides an overview of Finite State Machines (FSMs), including their representation, timing, and performance, as well as the differences between Moore and Mealy machines. It discusses the use of state diagrams and ASM charts for FSM design, and highlights VHDL descriptions and state assignment techniques. Additionally, it compares the advantages and disadvantages of Moore and Mealy machines in various applications.

Uploaded by

Asma Khider
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Finite State Machine

Based on Pong P. Chu Slides


Outline
1. Overview
2. FSM representation
3. Timing and performance of an FSM
4. Moore machine versus Mealy machine
5. VHDL description of FSMs
6. State assignment
7. Moore output buffering
8. FSM design examples

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1. Overview on FSM

• Contain “random” logic in next-state logic


• Used mainly used as a controller in a large
system
• Mealy vs Moore output

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2. Representation of FSM

• State diagram

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• E.g.
a memory
controller

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• ASM (algorithmic state machine) chart
– Flowchart-like diagram
– Provide the same info as an FSM
– More descriptive, better for complex description
– ASM block
• One state box
• One ore more optional decision boxes: with T or F exit path
• One or more conditional output boxes: for Mealy output

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State diagram and ASM chart
conversion
• E.g. 1.

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• E.g. 2.

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• E.g. 3.

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• E.g. 4.

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• E.g. 6.

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• Difference between a regular flowchart and ASM
chart:
– Transition governed by clock
– Transition done between ASM blocks
• Basic rules:
– For a given input combination, there is one unique exit
path from the current ASM block
– The exit path of an ASM block must always lead to a
state box. The state box can be the state box of the
current ASM block or a state box of another ASM block.

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• Incorrect ASM charts:

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4. Moore vs Mealy output

• Moore machine:
– output is a function of state
• Mealy machine:
– output function of state and output
• From theoretical point of view
– Both machines have similar “computation
capability”
• Implication of FSM as a controller?

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• E.g., edge detection circuit
– A circuit to detect the rising edge of a slow “strobe”
input and generate a “short”
(about 1-clock period) output pulse.

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• Three designs:

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• Comparison
– Mealy machine uses fewer states
– Mealy machine responds faster
– Mealy machine may be transparent to glitches
• Which one is better?
• Types of control signal
– Edge sensitive
• E.g., enable signal of counter
• Both can be used but Mealy is faster
– Level sensitive
• E.g., write enable signal of SRAM
• Moore is preferred

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VHDL Description of FSM

• Follow the basic block diagram


• Code the next-state/output logic
according to the state diagram/ASM
chart
• Use enumerate data type for states

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• E.g. 6.

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