MUTHAYAMMAL ENGINEERING

COLLEGE
(An Autonomous Institution)
(Approved by AICTE, New Delhi, Accredited by NAAC & Affiliated to
Anna University) Rasipuram - 637 408, Namakkal Dist., Tamil Nadu

MUST KNOW CONCEPTS MKC

EC
E
2022-
2023
Course Code & Course : 21ECC07 & Microcontroller Based
Name Embedded System.
Year/Sem : II/IV

Notation Concept/Definition/ Units

[Link] Ter
(Symbol) Meaning/
m
Units/Equation/
Expression
UNIT-I : Introduction to Microprocessor and
Microcontroller
Fetches,decodes and executes
1. Microprocessor µP No units
instructions.
Perform one task and execute one
2. Microcontroller µC No units
specific application.
Computing system designed using a
3. Microcomputer - No units
microprocessor as its CPU.
Ancillary device used to put
4. Peripheral Devices - information into and get No units
information
out of the computer.
ROM permanently storing programs
5. Memory - No units
and RAM temporary storage.
The input, output devices and
6. Buses memory devices are connected to the No units
CPU by groups of lines.
Output line the microprocessor sends
7. Serial Output Data SOD No units
output serial data.
Input line the microprocessor accepts
8. Serial Input Data SID No units
serial data.
9. RESET OUT - It indicates that the CPU is being reset. No units
Return is used at the end of a
10. Return RET No units
subroutine.
Requesting the use of the address and
11. HOLD - No units
data Buses.

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 CPU received the Hold request and
12. Hold HLDA No units
will relinquish the buses in the
Acknowledgement
next clock cycle.
Store 8-bit data and perform
13. Accumulator A No units
arithmetic, logical operations.
Microprocessor identifies the operands
14. Addressing mode - for the instruction. No units
Hold the memory address of the next
15. Stack Pointer SP No units
instruction to be executed.
16-bit register which holds the address
16. Program Counter PC No units
of the top of stack.
Non-Maskable An interrupt which can be never be
17. - No units
Interrupts turned off.
18. An interrupt that can be turned off by
Maskable interrupts - No units
the programmer.
Transfer data to and from a
19. Direct Memory Access DMA memory subsystem, for high speed No units
data
transfer.
External signal that causes a
20. Interrupt - microprocessor to jump to a specific No units
subroutine
16 bit addressing register fetch any 8
21. Data point register DPTR No units
bit data from the data memory space.

Keeps current status of the arithmetic,

22. Program status word PSW No units
logic operations in different bits.
Timers are used to generate a time
23. Timers - No units
delay.
Count events happening outside the
24. Counters - No units
microcontroller.
The program makes use of symbolic
25. Mnemonics - No units
opcodes.
UNIT-II :PIC Microcontroller
Programmable device functions
26.
USART - and specification can be No units
determined by writing instructions
in its internal
registers.
One subdivision of the operation
27. T State - No units
performed in one clock period.
28. Identifier that is associated with first
Variable - No units
byte of data item.
Fetching the next instructions while
29. Pipelining - No units
the current instruction executes.
Edge triggered input, which causes a
30. Non Maskable
NMI type 2 interrupt, Maskable internally No units
Interrupt by software and transition from low
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 to
high.
Effective Address - Access a memory location it sends an No units
31. offset value to the BIU.

Parallel Gets a byte and sends all the bits in

32. Communication - that byte simultaneously to the No units
Interface external system.
Time required to translate assembly
33. Assemble Time - No units
code to object code.
String instructions to address the
34. String Addressing - No units
source and destination operand/data.
Protect the chip and the inter connect
35. Encapsulation - No units
technology to connect the chip
electrically to the printed circuit.
Instructions that are used for single bit
36. Single bit instructions - No units
operation.
Protect an application in case the
37. Watch Dog Timer - No units
controlling microcontroller begins to
run execute randomly.
Interrupts are re-enabled inside an
38. Nesting of Interrupts - No units
interrupt handler.
39. Obtain an accurate position control of
Stepper motor - No units
rotating shafts.
Microprocessor must wait until the
40. Key bouncing - No units
key reach to a steady state.
Total time required to convert an
41. Conversion Time - No units
analog signal into a digital output.
Process of completely dividing the
42. Memory Segmentation - physically available memory into No units
a
number of logical segments.
Provides the basic timing for processor
43. Clock Input - No units
operation and bus control activity
If more than one process is carried out
44. Multiprogramming - No units
at the same time.
Copies program into computer’s main
45. Loader - No units
memory at load time, begins the
program execution at execution time.
Parallel Gets a byte and sends all the bits in
46. - No units
Communication that byte simultaneously to the
Interface external system.
Internal flip flop to enable or disable
47. Interrupt Enable INTE No units
generation of INTR signal.
Output signal to interrupt the CPU to
48. Interrupt Request INTR No units
request the next data byte for output.
Interrupt Request Store all interrupt levels which are
49. IRR No units
Register requesting services.

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 Store all the interrupt levels which are
50. In-Service Register - No units
being serviced.
UNIT-III :ARM Cortex m3 Architecture and
Processor
Group of instructions written to No units
51. Subroutine -
perform a specific task.
Interrupt Service Breaks the normal sequence of
52. - No units
Routine execution of instructions & diverts its

When this instruction is executed, the

53. Disable Interrupt - No units
interrupts are Disabled.
Machine cycle executed to fetch
54. Opcode Fetch Cycle - No units
the opcode of an instruction
stored in
memory.
The data structure be accessed of first
Queue -
55. in and first out. No units

56. Collection of procedures that used in No units

Libraries -
other programs.
Move /read special register value into
57. MRS - No units
general purpose registers.
The interaction between hardware and
58. Operating System - No units
software is managed by a set of
programs.
MSR - Move/write general purpose registers No units
59. into special purpose registers.

Bit band operation Its supports allows a single load/store

60. - No units
operation to acess to a single data bit
It is superset of 32 bit ARM and 16 bit
61. Thumb instruction - No units
thumb instruction set.

Group of instruction is called

62. Instruction Set - No units
Instruction set.
MPU role is to define access rules for
63. Memory protection unit - No units
privilege and user access levels
Thread mode and handler mode
64. Modes - No units

65. Levels of operation - No units

Privilege, user
Thread mode - User access level
66. No units

67. Privilege level - No units

Software in a privileged access level can
access the system control space.

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 Ensure that chip operate only when
68. Power on reset - No units
supply voltage is within specification.
Power supply goes below a specified
69. Brown out reset - No units
voltages (4V) it causes PIC to reset.

Analog to digital Converts analog signal into equivalent

70. ADC No units
Converter digital number.

Group of instructions written to

71. Subroutine - No units
perform a specific task.
System that helps to replace the
72. Look up table - No units
runtime computations.
Used to store the return program counter
73. Link register - No units
when a subroutine or function is called
All the external interrupt and most of the
74. Nested vector interrupt NVIC No units
system exceptions can be programmed to
different priority levels.
Enables consistent device support and
75. Common CMSIS No units
simple software interfaces to the
microcontroller
processor and its peripherals
software interface
standard
UNIT-IV :Introduction to Embedded System and Embedded Firmware

76. - It is an arrangement in which all its units No units

System
assemble and work
together according to the plan or
program.
- It is a combination of hardware and No units
77. Embedded
software, either fixed in capability or
System
programmable, designed for a specific
function
or functions within a larger system.
Components of -  Hardware, Application Software, No units
78. an Embedded  Real Time Operating Systems
System (RTOS)
-  Available System Memory, No units
79.
Constraints  Available Processor Speed,
 limit power dissipation
Classifications of -  Small Scale Embedded System, No units
81.
Embedded Systems  Medium Scale Embedded System,
 Sophisticated Embedded System
Applications of - Consumer electronics, Consumer
82. Embedded No units
products, Automobiles, Industrial
System process controllers &
avionics/defense
Quality Attributes -  Operational quality attributes
83. No units
of Embedded  Non-operational quality attributes
System
-  Response
84. No units
 Throughput
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 Operational Quality  Reliability
attributes  Maintainability
 Security
 Safety
-  Testability and Debug-ability
85. No units
 Evolvability
Non-operational
quality attributes  Portability
 Time to prototype and market
 Per unit and total cost
-  Application and domain specific, No units
86.  Tightly constrained,
Characteristics of
 Reactive and real time
Embedded System
 Operation in harsh environment
 Distributed
 Compact in size and light weight
-  General Purpose and Domain
87. No units
Specific Processors
Core of the  Microprocessors
Embedded  Microcontrollers
Systems  Digital Signal
Processors
 Programmable Logic Devices
(PLDs)
 Application Specific Integrated
Circuits (ASICs)
 Commercial off the shelf
Components (COTS)
-  A specific class of computer
88. No units
software that provides the low-
Firmware level control for the
device's specific hardware.
 Simply, it is the software
substituted for hardware and
stored in ROM.
- Much like a digital wristwatch, a
89. Real-time clock No units
real-time clock (RTC) keeps the time
and date in an embedded system.
-  Typical examples of devices
90. No units
containing firmware are
Common embedded systems (running
examples of embedded software), home and
fireware personal-use appliances,
computers, and computer
peripherals.
 Firmware is held in non-volatile
memory devices such as ROM,
EPROM, EEPROM, and Flash
memory.
- A brownout reset is a circuit that causes
91. Brownout reset No units
a computer processor to reset (or
circuit
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 reboot) in the event of a brownout,
which is a significant drop in the power
supply output
voltage.
- A power on reset circuit ensures the
92. No units
system power supply stabilizes at the
Reset circuit correct levels, the clocks of the
processors settle accurately, and that
the loading of the internal registers is
complete before the device actually
starts
working or gets powered up.
- A brownout, sometimes also called a
93. Brown-out No units
'sag', is a "dip" in the voltage level of
condition the electrical line.
When a brownout occurs, the voltage
drops from its normal
level to a lower voltage and then returns.
-  A watchdog timer (WDT) is a
94. Watchdog Timer No units
timer that monitors
microcontroller (MCU)
programs to see if they are out
of control
-  Low-level firmware,
95. Types of firmware No units
 High-level firmware, and
Subsystem
Function of - Its main function is to protect the
96. watchdog timer system malfunctions. No units
Embedded firmware -  Super loop-based approach,
97. design No units
 Operating system based approach
approaches
-  Firmware assumes an
98. No units
intermediary role between the
hardware and software –
Functions of
including potential future
firmware
upgrades of the software.
 Some firmware (such as the BIOS
on a PC) does the job of booting
up a computer by initialising the
hardware components and
loading the operating
system.
-  Efficient Code Memory & Data
Advantages of Memory Usage (Memory
99. assembly language Optimization)
programming  High Performance
 Low level hardware access
 Code reverse engineering
High Level -  Subset of C (Embedded C) o
100. Language for Subset of C++ (Embedded C++)
Embedded  Any other high-level language
firmware
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 development with supported Cross-compiler
UNIT-V : RTOS based Embedded System Design

- Real Time Operating System is an OS No units

101. RTOS for embedded
systems, as these have real time
programming issues to solve.
- A computational unit that processes on No units
Processes
102. a CPU and whose
state changes under the control of kernel
of an OS.
- Process Control Block is a data No units
103. PCB
structure having the
information using which the OS controls
the process state.
- A process or sub process within a No units
104. Thread process that has its own PC, its own SP
and stack, its own priority parameter
for its
scheduling.
- Task is a set of computations or actions No units
Task that processes on a
105.
CPU under control of a scheduling kernel.
-  Idle state, No units
106.  Ready state,
Task states  Running State,
 Blocked State,
 Deleted State
Characteristics of - A task is a function, which executes on No units
107. Task scheduling. A task
can wait as well as post the events or
signals or messages.
- An output from one task passed to No units
108. Inter process
another task through the scheduler and
communication
use of signals, exception, semaphore,
queues,
mailbox, pipes, sockets, and RPC.
- Semaphore provides a mechanism to let No units
109. Semaphore a task wait till another finishes. It is a
way of synchronizing concurrent
processing operations.
- Mutex is a semaphore that gives at an No units
110. Mutex instance two tasks
mutually exclusive access to resources.
-  Facilitating easy sharing of No units
111.
resources,
Goals of RTOS
 Facilitating easy implantation of
the application software,
 Maximizing system performance
- It is a computer program at the core of a No units
112.
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 Kernel computer's operating system with
complete control over everything in the
system
-  Process management, No units
113.
 Process creation to deletion,
 Processing resource requests
Functions of a Scheduling,
kernel  IPC,
 Memory management,
 I/O management,
 Device management
- Once the CPU has been allocated to a No units
114. Non-preemptive
process, the process keeps the CPU
scheduling
until it releases the CPU either by
terminating or switching to the waiting
state.
- Preemptive scheduling can preempt a No units
115. Preemptive process which is
scheduling utilizing the CPU in between its
execution and give the CPU to another
process.
116. Two important -  µCOS No units
RTOS  VxWorks
- Vxworks is a popular Real-time multi- No units
117. Vxworks tasking operating
system for embedded microprocessors
and systems.
-  Preemptive, No units
118. Features of  Portable,
µC/OS II  Scalable,
 Multitasking
-  Automobiles, No units
119.
 Avionics,
Application for the  Consumer electronics
VxWorks RTOS  Medical devices,
 Military,
 Aerospace,
 Networking
-  High performance, No units
120. Features of
 Host and target-based
VxWorks
development approach,
 Supports advanced processor
architecture.
-  System level, Task service No units
121.
Basic functions of µCOS function,
 Task delay,
 Memory allocation and
partitioning,
 IPCs,
 mailbox and queues
- Cameras that we use today are smart No units
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122. Digital camera and have a lot of
features that were not present in early
cameras all because of embedded
system used in them
- Debugging is the process of finding and No units
123. Debug resolving defects or
problems within a computer program
that prevent correct operation of
computer software or a system.
- Handshaking is the exchange of No units
124. Handshaking information between two
modems and the resulting agreement
about which protocol to use that
precedes each telephone connection.
-  MRI and CT Scanner, No units
125.
 Sonography,
 Digital Flow Sensors,
Medial  Defibrillator,
application
 Blood Pressure and Glucose Test
Set,
 Fetal Heart Monitoring Machine,
 Wearable Device.
Placement Questions
Accumulator register, Temporary No units
126. Various Registers - register, Instruction register, Stack
Pointer, Program Counter No units
Sign flag, Zero flag, Auxiliary flag, No units
127. Various Flags -
Parity flag, Carry flag.
LIFO (Last In First Out) the last stored No units
128. Stack Used In 8051 -
information retrieved first.
129. Hardware Interrupts - TRAP, RST7.5, RST6.5, RST5.5, INTR. No units

130. Quality Factor - Reflects the lossness of a circuit. No units

Sixteen bit register used to point at the No units

131. Stack Pointer Register -
stack
Hardware software needed to connect No units
132. Interfacing -
devices together.
Minimize the no of instructions per No units
133. CISC Processor -
program.
Program counter Holds a location in memory of the next No units
134. -
step to be performed.
Trap input Trap responds to both edge sensitive No units
135. -
and level sensitive.
Hlt The processor stops functioning buses No units
136. -
driven to tri-state.
Hold States The processor goes into hold state but No units
137. -
the buses are not driven to tri-state.

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 Maximum clock 5 MHz is the Maximum clock
138. - No units
frequency 8051 frequency
clock frequency for 3 MHz is the maximum clock
139. - No units
8051 frequency
140. Low order Register - Flag is called as Low order register No units
Accumulator is called as high order
141. High order Register - No units
register
142. Nibble - 4-bit aggregation or half an octet No units
Temporary storage of data and
143. Cache memory - information between main memory No units
and CPU
Load Effective Initializing register with an offset
144. - No units
Address address
Check whether a peripheral is ready
145. Ready pin - No units
to accept or transfer data
146. Handshake output - Processor will load a data to port No units
Modulator Breakup large program into
147. - No units
Programming manageable unit
Instructions to the assembler
148. Directives - concerning the program No units
being assembled
Translate high level language program
149. Compiler - No units
into machine code
Process of interfacing memories to
150. Memory Mapping - No units
microprocessor

Faculty Team Prepared Signatures

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