Department of Electronics and Communication

Engineering

Digital Electronics
(24ETECES204U/24EMECES204U)

Lecture Notes

B.Tech (I YEAR - II SEM)

(2024-25)
 DIGITAL ELECTRONICS

Department of Electronics and Communication

Engineering

Digital Electronics
(24ETECES204U/24EMECES204U)

COMBINATIONAL LOGIC

Module 3

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Unit 1- Boolean algebra And Logic Gates (9 Hrs)

Digital Systems, Binary Numbers, Octal and Hexadecimal Numbers, Number Base Conversions,
Signed Binary Numbers, Complements, One’s and Two’s complement arithmetic, binary codes
(BCD, Gray, and Xcess-3), Logic gates, Universal gates, Implementation of Boolean function
using universal gates.

Unit 2- Gate-Level Minimization (9 Hrs)

Boolean algebra: Basic theorems and properties, Canonical and Standard forms. Standard
Representation of a logic function, Sum of Product & Product of Sum Simplifications, The K-Map
Method, Don’t care conditions, Three – variable, Four – variable K-maps, Quine-McCluskey
Minimization method.

Unit 3- Combinational Logic (9 Hrs)

Combinational circuits, Binary Adder, Binary Subtractor, 2-bit magnitude comparator, Decoders,
Encoders, Multiplexer, Demultiplexer, Code Converters (Binary to Gray, Gray to Binary, Xcess-3
to BCD, BCD to Xcess-3).

Unit 4- Sequential Logic Circuits (9 Hrs)

Sequential circuits, Latches, Flip-Flops SR, JK, D and T flip flops, Registers, Shift Registers,
Synchronous and Asynchronous Counters, Ring counter, Johnson Counter.

Unit 5- Semiconductor memories and Programmable logic devices (9 Hrs)

Classification and characteristics of memories, sequential memory, read only memory (ROM) and
its types, Read and write memory (RAM) and its types, Programmable logic array, Programmable
array logic

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Syllabus Module-: Combinational Logic (9hrs)

Combinational circuits, Binary Adder, Binary Subtractor, 2-bit magnitude comparator, Decoders,
Encoders, Multiplexer, Demultiplexer, Code Converters (Binary to Gray, Gray to Binary, Xcess-3
to BCD, BCD to Xcess-3).

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BREAKDOWN OF TOPICS IN SEQUENCE IN MODULE 3

TOPIC No. CONTENT PAGE NO.

3.1 COMBINATIONAL CIRCUITS 5

3.1.1 Analysis And Design Procedure Of a Combinational
Circuit
3.1.1.1 Analysis Procedure
3.1.1.2 Design Procedure

3.2 BINARY ADDER

3.2.1 Half Adder
3.2.2 Full Adder
3.2.2.1 Implementation Of Full Adder With Two Half Adders
3.2.3 Parallel Binary Adders
3.2.4 Carry Look-Ahead Adder
3.2.4.1 4 - Bit Carry Look Ahead Adder
3.2.4.2 Applications And Examples
3.3 BINARY SUBTRACTOR
3.3.1 Half Subtractor
3.3.2 Full Subtractor
3.3.3 Parallel Subtractor
3.3.4 Parallel Binary Adder – Subtractor
3.4 BINARY COMPARATOR
3.2.1 2 – Bit Magnitude Comparator
3.2.2 4 – Bit Magnitude Comparator
3.2.3 Applications
3.5 DECODER
3.5.1 The Basic Binary Decoder
3.5.2 3 To 8 Line Decoder
3.5.2.1 Decoders With Enable Inputs
3.5.3 Boolean Function Implementation Using Decoder
3.5.4 Application Of Decoder Circuits
3.6 ENCODER
3.6.1 Octal To Binary Encoder
3.6.2 Priority Encoder
3.7 MULTIPLEXER
3.7.1 Boolean Function Implementation Using Multiplexer
3.8 DEMULTIPLEXER
3.8.1 1 To 4 Demultiplexer
3.8.2 4 Line To 16 Line Decoder As a Demultiplexer
3.9 CODE CONVERTERS
3.9.1 Binary To Gray Code
3.9.2 Gray To Binary Code
3.9.3 BCD To Excess-3 Code
3.9.4 Excess-3 To BCD Code

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3.1 COMBINATIONAL CIRCUITS

Logic circuits for digital systems may be combinational or sequential. A combinational circuit
consists of logic gates whose outputs at any time are determined from only the present combination
of inputs. A combinational circuit performs an operation that can be specified logically by a set of
Boolean functions.
The three basic logic functions AND, OR, and NOT can be combined to form various other types of
more complex logic functions, such as comparison, arithmetic, code conversion, encoding,
decoding, data selection, counting, and storage. A digital system is an arrangement of the individual
logic functions connected to perform a specified operation or produce a defined output. This section
provides an overview of important logic functions and illustrates how they can be used in a specific
system.
A combinational circuit, also called a combinational logic circuit, is a digital electronic circuit
whose output is determined by present inputs only. The output of a combinational logic circuit does
not depend on the history of the circuit operation. In other words, a combinational circuit is a digital
logic circuit whose output depends only on the present input values and does not depend on any
feedback or previous input or output values.
Block diagram of combinational logic:

Figure 3.1: Block Diagram of Combinational Logic

For n input variables, there are 2n possible combinations of the binary inputs. For each possible
input combination, there is one possible value for each output variable. Thus, a combinational
circuit can be specified with a truth table that lists the output values for each combination of input
variables. A combinational circuit also can be described by m Boolean functions, one for each
output variable. Each output function is expressed in terms of the n input variables.

3.1.1 Analysis and Design Procedure of a Combinational Circuit

The diagram of a combinational circuit has logic gates with no feedback paths or memory elements .
To obtain the output Boolean functions from a logic diagram, we proceed as follows:
3.1.1.1Analysis Procedure
 Label all gate outputs that are a function of input variables with arbitrary symbols— but
with meaningful names.
 Determine the Boolean functions for each gate output. Label the gates that are a function of
input variables and previously labeled gates with other arbitrary symbols.
 Find the Boolean functions for these gates. Repeat the process outlined in step 2 until the
outputs of the circuit are obtained.
 By repeated substitution of previously defined functions, obtain the output Boolean
functions in terms of input variables.

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Example:
Logic Diagram:

Figure 3.2: Logic Diagram for Analysis Example

Boolean Function: 𝐹1 = T2+T3
𝐹2 =AB+AC+BC
̅̅̅̅
𝐹2 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶
T3 = T1+𝐹2 ̅̅̅̅
T2 =ABC
T1 =A+B+C
Truth table:
Table 3.1: Truth Table of above Logic Diagram
A B C F2 ̅̅̅̅ 𝑭𝟐 T1 T2 T3 F1
0 0 0 0 1 0 0 0 0
0 0 1 0 1 1 0 1 1
0 1 0 0 1 1 0 1 1
0 1 1 1 0 1 0 0 0
1 0 0 0 1 1 0 1 1
1 0 1 1 0 1 0 0 0
1 1 0 1 0 1 0 0 0
1 1 1 1 0 1 1 0 1

3.1.1.2 Design Procedure

 From the specifications of the circuit, determine the required number of inputs and outputs
and assign a symbol to each.
 Derive the truth table that defines the required relationship between inputs and outputs.
 Obtain the simplified Boolean functions for each output as a function of the input variables.
Draw the logic diagram and verify the correctness of the design (manually or by simulation).

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Example:
Design a combinational logic circuit with three inputs, the output is at logic 1 when more than one
input is at logic 1.
Step1: Truth table:
Assume A, B, C, are inputs and Y is output.
Table 3.2: Truth Table of an Example
Inputs Output
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Step2: K- Map Simplification:

Step3: Boolean Function: Y = AC + BC + AB

Step4: Logic diagram:

3.2 BINARY ADDER

Adders are important in computers and also in other types of digital systems in which numerical
data are processed. An understanding of the basic adder operation is fundamental to the study of
digital systems. In this section, the half-adder, the full-adder, Binary adder, Ripple adder and
Carry Look-Ahead adders are introduced.

3.2.1 Half Adder

The most basic arithmetic operation is the addition of two binary digits. This simple addition
consists of four possible elementary operations: 0 + 0 = 0
0+1=1
1+0=1
1 + 1 = 10
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The binary addition consists of two digits. The higher significant bit of this result is called a carry
and lower significant bit is called sum. The above operations are performed by a logic circuit called
a half-adder.
Logic symbol:

Figure 3.3: Half Adder Logic Symbol

Truth Table: K-Map Simplification:
Table 3.3: Truth Table of a Half Adder
Input Output

A B Ʃ Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Boolean Function:
Sum/Ʃ = 𝐴𝐵̅ + 𝐴̅𝐵 = A⨁B
Carry/Cout = AB
Logic Diagram:

Figure 3.4: Implementation of Half Adder

3.2.2 Full-Adder
A full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of three
inputs and two outputs. Two of the input variables, denoted by A and B, represent the two
significant bits to be added. The third input, Cin, represents the carry from the previous lower
significant position.
The basic difference between a full-adder and a half-adder is that the full-adder accepts an input
carry. A logic symbol for a full-adder is shown in Figure 3.5 and the truth table in Table 3.4 shows
the operation of a full-adder
Logic symbol:

Figure 3.5: Full-Adder Logic Symbol

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Truth Table: K- Map Simplification:

Table 3.4: Truth Table of a Full Adder
Inputs Outputs
A B Cin Ʃ Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Boolean Function:
Ʃ = Sum = 𝐴̅𝐵̅𝐶𝑖𝑛 + 𝐴̅𝐵𝐶
̅̅̅̅ ̅ ̅̅̅̅
𝑖𝑛 + 𝐴𝐵 𝐶𝑖𝑛 + 𝐴𝐵𝐶𝑖𝑛
= A⨁B⨁C
Cout = AB+ACin+BCin

Logic Diagram:

Figure 3.6: Implementation of Full-Adder

3.2.2.1 Implementation of full adder with two half adders and an OR gate:

Figure 3.7: Implementation of Full Adder with two Half Adders and an OR gate

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3.2.3 Parallel Binary Adders

Two or more full-adders are connected to form parallel binary adders. A single full-adder is capable
of adding two 1-bit numbers and an input carry. To add binary numbers with more than one bit, you
must use additional full-adders. It can be constructed with full adders connected in cascade with the
carry output of each full adder is connected to the carry input of the next higher-order adder as
indicated. These are called internal carries. To add two binary numbers, a full-adder (FA) is
required for each bit in the numbers. So for 2-bit numbers, two full adders are needed, for 4-bit
numbers, four full adders are used and addition of n-bit numbers requires a chain of n full adders.

Example: Addition of two 2-bit numbers

Example: Addition of two 3-bit numbers

A2 A1 A0
+ B2 B1 B0
S3 S2 S1 S0

Example: Addition of two 4-bit numbers

Logic symbol: Logic diagram:

Figure 3.8a: A 4-bit Parallel Adder Logic Symbol Figure 3.8b: A 4-bit Parallel Adder Logic Diagram

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3.2.4 Carry Look-Ahead Adder

Since each bit of the sum output depends on the value of the input carry, the value of S i at any given
stage in the adder will be in its steady-state final value only after the input carry to that stage has
been propagated. In this regard, consider output S3 in Fig. 3.8b. Inputs A3 and B3 are available as
soon as input signals are applied to the adder. However, input carry C 3 does not settle to its final
value until C2 is available from the previous stage. Similarly, C2 has to wait for C1 and so on down
to C0. Thus, only after the carry propagates and ripples through all stages will the last output S 3 and
carry C4 settle to their final correct value.
The speed with which an addition can be performed is limited by the time required for the carries to
propagate, or ripple, through all the stages of a parallel adder. One method of speeding up the
addition process by eliminating this ripple carry delay is called look-ahead carry addition. The look-
ahead carry adder anticipates the output carry of each stage, and based on the inputs, produces the
output carry by either carry generation or carry propagation.
Truth table:
Table 3.5: Truth Table of a Carry Look-Ahead Adder
A B Cin Sum Carry Condition
0 0 0 0 0
0 0 1 1 0 No carry generated
0 1 0 1 0
0 1 1 0 1 Carry propagated
1 0 0 1 0 No carry
1 0 1 0 1 Carry propagated
1 1 0 0 1 Carry generated
1 1 1 1 0

Analyzing the Full adder Truth table:

Carry Generator = Gi = Ai Bi
Carry Propagation = Pi = Ai ⨁ Bi
Thus we can rewrite the Boolean function of the full adder in terms of Carry generator (Gi ) and
Carry propagation (Pi) as:
Sum = Si = Pi ⨁ Ci
Carry = Ci = Gi + Pi Ci
Logic diagram of a Full adder with P and G

Figure 3.9: Carry Generation and Carry Propagation

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3.2.4.1 4- Bit Carry Look Ahead Adder:

We now write the Boolean functions for the carry outputs of each stage and substitute the value of
each Ci from the previous equations:
C0 = input carry
C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1 (G0 + P0C0) = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 = P2P1P0C0
Logic diagram:

Figure 3.10: Logic Diagram of Carry Look-Ahead Generator

Four-bit Adder with Carry Look ahead:

Figure 3.11: Four-bit Adder with Carry Look Ahead

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Applications: High- Speed Computing: CLAs are utilized in processors and digital systems where
rapid arithmetic operations are crucial.

Example: Use the 4-bit parallel adder to find the sum and output carry for the addition of the
following two 4-bit numbers if the input carry (Cn-1) is 0.
A4 A3A2A1 = 1100 and B4B3B2B1 = 1100
Solution
For n = 1: A1 = 0, B1 = 0, and Cn-1 = 0.
Ʃ1 = 0 and C1 = 0
For n = 2: A2 = 0, B2 = 0, and Cn-1 = 0.
Ʃ2 = 0 and C2 = 0
For n = 3: A3 = 1, B3 = 1, and Cn-1 = 0.
Ʃ3 = 0 and C3 = 1
For n = 4: A4 = 1, B4 = 1, and Cn-1 = 1.
Ʃ4 = 1 and C4 = 1 C4 becomes the output carry; the sum of 1100 and 1100 is 11000

3.3 BINARY SUBTRACTOR

Subtractor is the logic circuit which is used to subtract two binary numbers (digit) and provides
Difference and Borrow as a output.

3.3.1 Half Subtractor

A half subtractor is a combination circuit with two inputs (A and B) and two outputs (difference and
borrow). It produces the difference between the two binary bits at the input and also produces an
output (Borrow) to indicate if a 1 has been borrowed. In binary subtraction (A-B), A is called a
Minuend bit and B is called a Subtrahend bit.
Truth table:
Table 3.6: Truth Table of a Half Subtractor
Inputs Outputs K- Map Simplification:

A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Boolean Function:
Difference = D = 𝐴𝐵̅ + 𝐴̅𝐵 = A⨁B
Borrow = 𝐴̅B
Logic Diagram:

Figure 3.12 Implementation of Half Subtractor

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3.3.2 Full Subtractor

The full subtractor is also a combinational circuit with three inputs A, B, and B in, and two outputs D
and Bout. Here, A is the minuend bit, B is the subtrahend bit, Bin is the previous borrow bit produced
by the previous stage, D is the difference output and Bout is the borrow output.

Truth Table:
Table 3.7: Truth Table of a Full Subtractor
Inputs Outputs K- Map Simplification:
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Boolean Function:
D = 𝐴̅ 𝐵̅ Bin + 𝐴̅ B 𝐵𝑖𝑛
̅̅̅̅̅ + A 𝐵̅ 𝐵𝑖𝑛
̅̅̅̅̅ + ABBin
= A⨁B⨁Bin
Bout = 𝐴̅ Bin+𝐴̅ B+BBin
Logic Diagram:

Figure 3.13: Implementation of Full Subtractor

3.3.3 Four Bit Parallel Binary Subtractor

The subtraction operation can be performed using 1’s and 2’s complement addition, so we can
design Full subtractor using Full Adder.

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Figure 3.14: Four Bit Subtractor

3.3.4 Parallel Binary Adder – Subtractor

The addition and subtraction operations can be perform using a common adder circuit, where a EX-
OR gate is connected in the second input along with the mode selection bit M. if M=0 the circuit act
as a adder, M=1 then substractor. If M=0 then output of the EX-OR gate is B act as adder, if M=1
then B act as a subtractor. Each exclusive-OR gate receives input M and one of the inputs of B.
When M = 0, we have B⨁0 = B. The full adders receive the value of B, the input carry is 0, and the
circuit performs A plus B. When M = 1, we have B ⨁ 1 = B and C0 = 1. The B inputs are all
complemented and a 1 is added through the input carry. The circuit performs the operation A plus
the 2’s complement of B. (The exclusive-OR with output V is for detecting an overflow.)

Figure 3.15: Four-Bit Adder–Subtractor

Example: The adder–subtractor circuit of Figure.3.15 has the following values for mode input M
and data inputs A and B.
M A B
a) 0 0111 0110
b) 0 1000 1001
c) 1 1100 1000
d) 1 0101 1010
e) 1 0000 0001
In each case, determine the values of the four SUM outputs, the carry C, and overflow V.

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3.4 COMPARATOR
The comparison of two numbers is an operation that determines whether one number is greater than,
less than, or equal to the other number. A magnitude comparator is a combinational circuit that
compares two numbers A and B and determines their relative magnitudes. The outcome of the
comparison is specified by three binary variables that indicate whether A > B, A = B, or A < B.
The exclusive-NOR gate can be used as a basic comparator because its output is a 0 if the
two input bits are not equal and a 1 if the input bits are equal. Figure 3.16 shows the exclusive-NOR
gate as a 1-bit comparator

Figure: 3.16 Basic Comparator Operations

Truth table:
Table 3.8: Truth Table of a Comparator
Inputs Outputs K-Map Simplification:
A0 B0 L E G
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0

Boolean functions:
̅̅̅̅ B0
L = 𝐴0
̅̅̅̅ 𝐵0
E = 𝐴0 ̅̅̅̅̅ + 𝐴0 𝐵0
G = 𝐴0 ̅̅̅̅𝐵0
Logic diagram:

Figure 3.17: Implementation of 1-Bit Comparator

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3.4.1 2-Bit Magnitude Comparator

In order to compare binary numbers containing two bits each, an additional exclusive NOR gate is
necessary. The two least significant bits (LSBs) of the two numbers are compared by gate G1, and
the two most significant bits (MSBs) are compared by gate G2, as shown in Figure 3.18. If the two
numbers are equal, their corresponding bits are the same, and the output of each exclusive-NOR
gate is a 1. If the corresponding sets of bits are not equal, a 0 occurs on that exclusive-NOR gate
output.

Figure 3.18: Logic Diagram for Equality Comparison of two 2-bit numbers
The complete Logic diagram of 2-bit Magnitude Comparator is shown below if A= A1A0 and B=
B1B0.
Truth table:
Table 3.9: Truth Table of a 2-bit Magnitude Comparator
Inputs Output
A1 A0 B1 B0 A > B (G) A = B (E) A < B (L)
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

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K- Map Simplification:

Boolean functions:
Equal (A = B) ̅̅̅̅ ̅̅̅̅
E =𝐴0 𝐵0 ̅̅̅̅
𝐴1 ̅̅̅̅
𝐵1 + 𝐴0 ̅̅̅̅ 𝐴1 𝐵0 ̅̅̅̅
𝐵1 + 𝐴0 𝐴1 𝐵0 𝐵1 + ̅̅̅̅
𝐴0 𝐴1 ̅̅̅̅̅
𝐵0 𝐵1
̅̅̅̅ ̅̅̅̅
E = (𝐴0 𝐵0 + 𝐴0 𝐵0) (𝐴1 𝐵1 + 𝐴1 𝐵1) ̅̅̅̅ ̅̅̅̅
Ei = 𝐴𝑖𝐵i + 𝐴̅i𝐵̅i for i = 0, 1
E = E0E1
Greater (A > B) = G = A1𝐵̅1 + E1A0𝐵̅0
Less (A < B) = L = 𝐴̅1B1 + E1𝐴̅0 B0
Logic diagram:

Figure 3.19: Implementation of 2-Bit Comparator

3.4.2 4-Bit Magnitude Comparator
Consider two 4-bit numbers,
A = A3 A2 A1 A0
B = B3 B2 B1 B0
A and B are equal (A = B) if A3 = B3, A2 = B2, A1 = B1, and A0 = B0.
To determine whether (A > B) or (A < B), starting from the MSB, if the two bits are equal, then
compare the next lower significant pair of bits until a pair of unequal bits is reached.
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Boolean Function:
Ei = AiBi + 𝐴̅i𝐵̅i, for i = 0, 1, 2, 3
E = E0E1E2E3
G = (A > B) = A3𝐵3 ̅̅̅̅ + E3A2𝐵2̅̅̅̅̅+ E3E2A1𝐵1
̅̅̅̅ + E3E2E1A0𝐵0̅̅̅̅̅
L = (A < B) = ̅̅̅̅
𝐴3B3 + E3𝐴2 ̅̅̅̅B2 + E3E2𝐴1
̅̅̅̅B1 + E3E2E1𝐴0
̅̅̅̅B0
Logic Diagram:

Figure 3.20: Four-bit Magnitude Comparator

3.4.3 Applications of Comparators

Comparators are used in central processing units (CPUs) and microcontrollers (MCUs). These are
used in control applications in which the binary numbers representing physical variables such as
temperature, position, etc. are compared with a reference value.

3.5 DECODER
A decoder is a digital Combinational circuit that detects the presence of a specified combination of
bits (code) on its inputs and indicates the presence of that code by a specified output level. In its
general form, a decoder has n input lines to handle n bits and from one to 2n output lines to
indicate the presence of one or more n-bit combinations.
3.5.1 The Basic Binary Decoder
Suppose you need to determine when a binary 1001 occurs on the inputs of a digital circuit. An
AND gate can be used as the basic decoding element because it produces a HIGH output only when
all of its inputs are HIGH. Therefore, you must make sure that all of the inputs to the AND gate are
HIGH when the binary number 1001 occurs; this can be done by inverting the two middle bits (the
0s), as shown in Figure 3.21. When A0 = 1, A1 = 0, A2 = 0, and A3 = 1 are applied to the inputs.
A0 is the LSB and A3 is the MSB. In the representation of binary number.

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Figure 3.21: Decoding Logic for the Binary Code 1001 with an Active-HIGH Output
In order to decode all possible combinations of four bits, sixteen decoding gates are required (2 4 =
16). This type of decoder is commonly called either a 4-line-to-16-line decoder because there are
four inputs and sixteen outputs.

3.5.2 3 to 8 Line Decoder:

The three inputs are decoded into eight outputs, each representing one of the minterms of the three
input variables. The three inverters provide the complement of the inputs, and each one of the eight
AND gates generates one of the minterms. A particular application of this decoder is binary-to-
octal conversion. The input variables represent a binary number, and the outputs represent the eight
digits of a number in the octal number system
Truth table:
Table 3.10: Truth Table of a 3 to 8 line Decoder
Inputs Outputs
A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Boolean Function:
D0 = ̅̅̅̅
𝐴2 ̅̅̅̅
𝐴1 ̅̅̅̅
𝐴0
̅̅̅̅ ̅̅̅̅
D1 = 𝐴2 𝐴1 A0
̅̅̅̅ A1 𝐴0
D2 = 𝐴2 ̅̅̅̅
D3 =̅̅̅̅̅
𝐴2 A1 A0
D4 = A2 ̅̅̅̅
𝐴1 ̅̅̅̅
𝐴0
̅̅̅̅
D5 = A2 𝐴1 A0
D6 = A2 A1 𝐴0 ̅̅̅̅
D7 = A2 A1 A0

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Logic Diagram:

Figure 3.22: Three-to-Eight-Line Decoder

3.5.2.1 Decoders with enable inputs/ Design of 4 to 16 line decoder using 3 to 8 line Decoder:
Decoders with enable inputs can be connected together to form a larger decoder circuit. Figure 3.23
shows two 3-to-8-line decoders with enable inputs connected to form a 4-to-16-line decoder. When
w = 0, the top decoder is enabled and the other is disabled. The bottom decoder outputs are all 0’s,
and the top eight outputs generate minterms 0000 to 0111. When w = 1, the enable conditions are
reversed: The bottom decoder outputs generate minterms 1000 to 1111, while the outputs of the top
decoder are all 0’s. This example demonstrates the usefulness of enable inputs in decoders and other
combinational logic components. In general, enable inputs are a convenient feature for
interconnecting two or more standard components for the purpose of combining them into a similar
function with more inputs and outputs.
Truth table:
Table 3.11: Truth Table of a 4 to 16 line Decoder
Inputs Outputs
A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
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Logic diagram:

Figure 3.23: 4 x16 Decoder Constructed with two 3x 8 Decoders

3.5.3 Boolean Function Implementation Using Decoder

A decoder that generates the minterms of the function, together with an external OR gate that forms
their logical sum, provides a hardware implementation of the function. In this way, any
combinational circuit with n inputs and m outputs can be implemented with an n -to-2 n -line
decoder and m OR gates.
The procedure for implementing a combinational circuit by means of a decoder and OR gates
requires that the Boolean function for the circuit be expressed as a sum of minterms. A decoder is
then chosen that generates all the minterms of the input variables. The inputs to each OR gate are
selected from the decoder outputs according to the list of minterms of each function.
Example: Implementation of a full adder with a decoder
S(x, y, z) = Ʃ (1, 2, 4, 7)
C(x, y, z) = Ʃ (3, 5, 6, 7)
Since there are three inputs and a total of eight minterms, we need a three-to-eight-line decoder. The
implementation is shown in Fig. 3.5.4. The decoder generates the eight minterms for x, y, and z.
The OR gate for output S forms the logical sum of minterms 1, 2, 4, and 7. The OR gate for output
C forms the logical sum of minterms 3, 5, 6, and 7.

Figure 3.24: Implementation of a Full Adder with a Decoder

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Example:
BCD-to-Decimal Decoder: The BCD-to-decimal decoder converts each BCD code (8421 code)
into one of ten possible decimal digit indications. It is frequently referred as a 4-line-to-10-line
decoder or a 1-of-10 decoder. The method of implementation is the same as the decoder previously
discussed, except that only ten decoding gates are required because the BCD code represents only
the ten decimal digits 0 through 9. A list of the ten BCD codes and their corresponding decoding
functions is given in following Table. Each of these decoding functions is implemented with NAND
gates to provide active-LOW outputs. If an active-HIGH output is required, AND gates are used for
decoding.
Truth table: Logic diagram:

Example:
Seven-Segment Display Decoder: The decoder is seven segment display decoders. Decoder
converts the binary codes to alphanumeric codes to be displayed in the seven-segment display. A
decoder in 7-segment display converts input signals into its corresponding control signal to the
LEDs (seven LEDs from a to g) present in the seven-segment display.
If we want to display any number, then the decoder selects the LEDs to be turned on using the
given number which results in displaying the given number in the seven-segment display. The 7-
segment display decoders are used in digital clocks, voltmeters and ammeters etc. The below
image represents the decoder to implement seven segment display

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3.5.4 Other Application of Decoder Circuits

Bar Code Scanner:

The decoders are one of the important components of the bar code scanner. It decodes the lines in
the bar codes and to the desired item code so that we can get the information about the item. The
decoder in barcode scanners helps in data interpretations, error correction and detection, inventory
management, delivery and shipping operations and billing systems.
The decoders present in the bar code scanners decodes the information of the item which helps in
billing and inventory management of goods. It also keeps track of the shipping and delivery of
goods by decoding the barcodes on shipping boxes.

Television Remote Control:

The remote-control devices like televisions, air conditioners have their own internal decoders
which decodes the signal generated when any button in the remote is pressed and makes the
desired action.

Traffic Light Control:

The decoders are an important part of the traffic light control systems. The decoder in these
systems helps to control sequence of traffic light and is used in dynamic traffic light control. The
decoder control the sequence of the traffic lights by decoding input signals and decides which
light should be ON at particular time. Decoder is also used in managing the timing and color of
the traffic lights, to reduce the traffic flow and congestion based on the information provided by
sensors.

Security Systems:
Decoders play an important role in the security systems. The decoders are used in various security
systems like alarm system, video processing system, CCTV cameras and many more. Decoders
are used to convert the digital signal of the videos to analog signals that can be displayed in the
monitors. It is also used activate alarms by decoding the signals received from the sensors.
Decoders are also used in upgrading the security systems

3.6 ENCODER
An encoder is a combinational logic circuit that essentially performs a “reverse” decoder function.
An encoder accepts an active level on one of its inputs representing a digit, such as a decimal or
octal digit, and converts it to a coded output, such as BCD or binary. Encoders can also be devised
to encode various symbols and alphabetic characters. The process of converting from familiar
symbols or numbers to a coded format is called encoding. It has maximum of 2n input lines and ‘n’
output lines. It will produce a binary code equivalent to the input, which is active High. Therefore,
the encoder encodes 2n input lines with ‘n’ bits. It is optional to represent the enable signal in
encoders.

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3.6.1 Octal-To-Binary Encoder

It has eight inputs (one for each of the octal digits) and three outputs that generate the
corresponding binary number. It is assumed that only one input has a value of 1 at any given time.
Truth table:
Table 3.12: Truth Table of an Octal to Binary Encoder
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 A2 A1 A0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

Boolean Function:
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7
The encoder can be implemented with three OR gates.
Logic diagram:

Figure 3.25: Implementation of Encoder

3.6.2 Priority Encoder
If two inputs are active simultaneously, the output produces an undefined combination. We
can establish an input priority to ensure that only one input is encoded. Another ambiguity in the
octal-to-binary encoder is that an output with all 0’s is generated when all the inputs are 0; the
output is the same as when D0 is equal to 1. The operation of the priority encoder is such that if two
or more inputs are equal to 1 at the same time, the input having the highest priority will take
precedence. The truth table of a four-input priority encoder is given in Table 3.13.

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V=0 no valid inputs

V=1 valid inputs
X’s in output columns represent don’t-care conditions
X’s in the input columns are useful for representing a truth table in condensed form. Instead of
listing all 16 minterms of four variables. The truth table uses an X to represent either 1 or 0. For
example, X 100 represents the two minterms 0100 and 1100.
Truth table:
Table 3.13: Truth Table of a Priority Encoder
Inputs Outputs K- Map Simplification:
D0 D1 D2 D3 X Y V
0 0 0 0 x x 0
1 0 0 0 0 0 1
x 1 0 0 0 1 1
x x 1 0 1 0 1
x x x 1 1 1 1
Boolean Functions:
X = D2 + D3
Y = D3 + D1 ̅̅̅̅
𝐷2
V = D0 + D1 + D2 + D3
Logic diagram:

Figure: 3.26: Implementation of Priority Encoder

3.7 MULTIPLEXER
A multiplexer (MUX) is a device that allows digital information from several sources to be routed
onto a single line for transmission over that line to a common destination. The basic multiplexer has
several data-input lines and a single output line. It also has data-select inputs, which permit digital
data on any one of the inputs to be switched to the output line. Multiplexers are also known as data
selectors. Normally, there are 2n input lines and n selection lines whose bit combinations determine
which input is selected. A logic symbol for a 4-input multiplexer (MUX) is shown in Figure 3.27.
Notice that there are two data-select lines because with two select bits, any one of the four data-
input lines can be selected.

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Logic symbol: 4x1 Mux

Figure 3.27: Logic Symbol for a 1-of-4 Data Selector/Multiplexer

Truth table:
Table 3.14: Truth Table of a
Select inputs Output
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

Boolean Function:
The data output is equal to the state of the selected data input. You can therefore, derive a logic
expression for the output in terms of the data input and the select inputs.
The data output is equal to D0 only if S1 = 0 and S0 = 0: Y = D0S1S0 .
The data output is equal to D1 only if S1 = 0 and S0 = 1: Y = D1S1S0 .
The data output is equal to D2 only if S1 = 1 and S0 = 0: Y = D2S1S0 .
The data output is equal to D3 only if S1 = 1 and S0 = 1: Y = D3S1S0 .
When these terms are ORed, the total expression for the data output is
Y = D0S1S0 + D1S1S0 + D2S1S0 + D3S1S0
Logic diagram:

Figure 3.28: Logic Diagram for a 4-Input Multiplexer

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Applications: Multiplexers find application in various fields such as telecommunications, data

communication systems, analog-to-digital converters, and memory addressing. They are used to
efficiently combine multiple input signals onto a single transmission line or channel.
3.7.1 Boolean Function Implementation Using Multiplexer
Implementing a Boolean function of n variables with a multiplexer that has n-1 selection inputs.
The first n-1 variables of the function are connected to the selection inputs of the multiplexer.
The remaining single variable of the function is used for the data inputs. If the single variable is
denoted by z, each data input of the multiplexer will be z, z’, 1 or 0.

Example: Implement F (x, y, z) = Ʃ (1, 2, 6, 7) using Multiplexer.

Solution
This function of three variables can be implemented with a four-to-one-line multiplexer as shown in
Figure 3.29. The two variables x and y are applied to the selection lines in that order; x is connected
to the S1 input and y to the S0 input. The values for the data input lines are determined from the
truth table of the function. When xy = 00, output F is equal to z because F = 0 when z = 0 and F = 1
when z = 1. This requires that variable z be applied to data input 0. The operation of the multiplexer
is such that when xy = 00, data input 0 has a path to the output, and that makes F equal to z. In a
similar fashion, we can determine the required input to data lines 1, 2, and 3 from the value of F
when xy = 01, 10, and 11, respectively.
Truth table: Multiplexer Implementation:
Table 3.15: Truth Table of a
Inputs Output
x y z F
0 0 0 0 F=z
0 0 1 1
0 1 0 1 F = z’
0 1 1 0
1 0 0 0 F=0
1 0 1 0
1 1 0 1 F=1
Figure 3.29: Implementing a Boolean function with a Multiplexer
1 1 1 1
Example:
Implement the logic function specified in Table 3.15 by using a 74HC151 8-input data
selector/multiplexer. Compare this method with a discreet logic gate implementation.
Inputs Output
A2 A1 A0 Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
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Solution
Notice from the truth table that Y is a 1 for the following input variable combinations: 001, 011,
101, and 110. For all other combinations, Y is 0. For this function to be implemented with the data
selector, the data input selected by each of the above-mentioned combinations must be connected to
a HIGH (5 V). All the other data inputs must be connected to a LOW (ground), as shown in Figure

The implementation of this function with logic gates would require four 3-input AND gates, one 4-
input OR gate, and three inverters unless the expression can be simplified.

Example: Use 74HC151s and any other logic necessary to multiplex 16 data lines onto a single
data-output line.
Solution
An expansion of two 74HC151s is shown in Figure. Four bits are required to select one of 16 data
inputs (24 = 16). In this application the Enable input is used as the most significant data-select bit.
When the MSB in the data-select code is LOW, the left 74HC151 is enabled, and one of the data
inputs (D0 through D7) is selected by the other three data select bits. When the data-select MSB is
HIGH, the right 74HC151 is enabled, and one of the data inputs (D8 through D15) is selected. The
selected input data are then passed through to the negative-OR gate and onto the single output line.

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Example:
Implement the logic function in following Table by using a 74HC151 8-input data selector/
multiplexer. Compare this method with a discreet logic gate implementation.
Inputs Output
Decimal digit A3 A2 A1 A0 Y
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 1
Solution:
The data-select inputs are A3A2A1 . In the first row of the table, A3A2A1 = 000 and Y = A0 . In
the second row, where A3A2A1 again is 000, Y = A0 . Thus, A0 is connected to the 0 input. In the
third row of the table, A3A2A1 = 001 and Y = A0 . Also, in the fourth row, when A3A2A1 again is
001, Y = A0 . Thus, A0 is inverted and connected to the 1 input. This analysis is continued until
each input is properly connected according to the specified rules. The implementation is shown in
below Figure.

If implemented with logic gates, the function would require as many as ten 4-input AND gates, one
10-input OR gate, and four inverters, although possible simplification would reduce this
requirement
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Example:
The data-input and data-select waveforms in Figure are applied to the four inputs multiplexer in
Figure 3.27. Determine the output waveform in relation to the inputs.

Solution:
The binary state of the data-select inputs during each interval determines which data input is
selected. Notice that the data-select inputs go through a repetitive binary sequence 00, 01, 10, 11,
00, 01, 10, 11, and so on. The resulting output waveform is shown in below Figure.

3.8 DEMULTIPLEXER
A Demultiplexer (DEMUX) basically reverses the multiplexing function. It takes digital
information from one line and distributes it to a given number of output lines. For this reason, the
demultiplexer is also known as a data distributor. It has 2 n outputs, n select lines, one input.

3.8.1 1-To-4 Demultiplexer

Logic Symbol:

Figure 3.30: Logic Symbol of Demultiplexer

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Truth table:
Table 3.16: Truth Table of a 1 to 4 Line Multiplexer
Input Select inputs Outputs
Din S1 S0 D0 D1 D2 D3
Din 0 0 1 0 0 0
Din 0 1 0 1 0 0
Din 1 0 0 0 1 0
Din 1 1 0 0 0 1

Boolean Function:
̅̅̅ 𝑆0
D0 = 𝑆1 ̅̅̅ Din
̅̅̅ S0 Din
D1 = 𝑆1
D2 = S1̅̅̅̅
𝑆0 Din
D3 = S1 S0 Din
Logic Diagram:

Figure 3.31: Implementation of DeMultiplexer

3.8.2 4-Line-To-16-Line Decoder as a Demultiplexer

We have already discussed a 4-line-to-16-line decoder (Lecture–5). This device and other
decoders can also be used in demultiplexing applications. The logic symbol for this device when
used as a demultiplexer is shown in Figure 3.30 In demultiplexer applications, the input lines are
used as the data-select lines. One of the chip select inputs is used as the data-input line, with the
other chip select input held LOW to enable the internal negative-AND gate at the bottom of the
diagram.

Figure 3.32: Implementation of 4-Line-to-16-Line Decoder as a Demultiplexer:

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Example: The serial data-input waveform (Data in) and data-select inputs (S0 and S1) are shown in
Figure below. Determine the data-output waveforms on D0 through D3 for the demultiplexer in
Figure 3.30

Solution:
Notice that the select lines go through a binary sequence so that each successive input bit is routed
to D0, D1, D2, and D3 in sequence, as shown by the output waveforms below.

3.9 CODE CONVERTERS

A symbolic representation of data/ information is called code. The base or radix of the binary
number is 2. Hence, it has two independent symbols. The symbols used are 0 and 1. A binary digit
is called as a bit. A binary number consists of sequence of bits, each of which is either a 0 or 1.
Each bit carries a weight based on its position relative to the binary point. The weight of each bit
position is one power of 2 greater than the weight of the position to its immediate right. Example of
binary number is 100011 which is equivalent to decimal number 35. The availability of a large
variety of codes for the same discrete elements of information results in the use of different codes
by different digital systems. It is some time necessary to use the output of one system as the input to
the other. The conversion circuit must be inserted between the two systems if each uses different
codes for the same information. Thus a code converter is a circuit that makes the two systems
compatible even though each uses the different code. In this section, we will examine some
methods of using combinational logic circuits to convert from one code to another example Binary
to Gray, Gray to Binary, Xcess-3 to BCD, and BCD to Xcess-3.
BCD Codes:
Numeric codes represent numeric information i.e. only numbers as a series of 0's and 1's. Numeric
codes used to represent decimal digits are called Binary Coded Decimal (BCD) codes. A BCD code
is one, in which the digits of a decimal number are encoded-one at a time into group of four binary
digits. There are a large number of BCD codes in order to represent decimal digits 0, 1, 2,....,9, it is
necessary to use a sequence of at least four binary digits. Such a sequence of binary digits which
represents a decimal digit is called code word.

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Gray Codes:
It is a non-weighted code; therefore, it is not a suitable for arithmetic operations. It is a cyclic code
because successive code words in this code differ in one bit position only i.e. it is a unit distance
code.
Application of Gray Code:
 In instrumentation and data acquisition system where linear or angular displacement is
measured.
 In shaft encoders, input-output devices, A/D converters and the other peripheral equipment.
Excess-3 Code: It is a non-weighted code. It is also a self-complementing BCD code used in
decimal arithmetic units. The Excess-3 code for the decimal number is performed in the same
manner as BCD except that decimal number 3 is added to the each decimal unit before encoding it
to binary.
3.9.1 Binary to Gray Code
Conversion between binary code and Gray code is sometimes useful. The following rules explain
how to convert from a binary number to a Gray code word:
 The most significant bit (left-most) in the Gray code is the same as the corresponding MSB
in the binary number.
 Going from left to right, add each adjacent pair of binary code bits to get the next Gray code
bit. Discard carries. For example, the conversion of the binary number 10110 to Gray code
is as follows:

Therefore the Gray code is 11101.

Truth table:
Table 3.17: Truth Table of a 3-bit Binary to Gray code Converter
Inputs Outputs
B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

K-Map Simplification:

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Boolean Function:
G2 = B2
G1 = ̅̅̅̅
𝐵2 B1 + B2 ̅̅̅̅
𝐵1 = B2 ⨁ B1
G0 = 𝐵1 B0 + B1̅̅̅̅̅
̅̅̅̅̅ 𝐵0 = B1 ⨁ B0
Logic diagram:

Figure 3.33: Implementation of 3-bit Binary to Gray code Converter

3.9.2 Gray-To-Binary Code Conversion
To convert from Gray code to binary, use a similar method; however, there are some differences.
The following rules apply:
 The most significant bit (left-most) in the binary code is the same as the corresponding bit in
the Gray code.
 Add each binary code bit generated to the Gray code bit in the next adjacent position.
Discard carries. For example, the conversion of the Gray code word 11011 to binary is as
follows:

The binary number is 10010.

Truth table:
Table 3.18: Truth Table of a Gray to Binary Code
Inputs Outputs
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
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Boolean functions:
B3 = G3
B2 = B3 ⨁ G2
B1 = B2 ⨁ G1
B0 = B1 ⨁ G0
Logic diagram:

Figure 3.34: Implementation of 4-Bit Gray-to-Binary Code Converter

3.9.3 BCD to Xcess-3 Code

The bit combinations assigned to the BCD and excess-3 codes are studied in the first module. Since
each code uses four bits to represent a decimal digit, there must be four input variables and four
output variables. We designate the four input binary variables by the symbols A, B, C, and D, and
the four output variables by W, X, Y, and Z. The truth table relating the input and output variables
is shown in Table 3.19.
Truth table:
Table 3.19: Truth Table of a BCD to Xcess-3
Input BCD Output Xcess-3
A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

Note that four binary variables may have 16 bit combinations, but only 10 are listed in the truth
table. The six bit combinations not listed for the input variables are don’t-care combinations. These
values have no meaning in BCD and we assume that they will never occur in actual operation of the
circuit. Therefore, we are at liberty to assign to the output variables either a 1 or a 0, whichever
gives a simpler circuit.

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K-Map Simplification:

The Boolean expressions derived from the K-maps are

Z=𝐷 ̅
̅ = CD + ̅̅̅̅̅̅̅̅̅̅̅̅
Y = CD + 𝐶̅ 𝐷 (𝐶 + 𝐷)
X = 𝐵C + 𝐵D + B𝐶 𝐷 = 𝐵̅(C + D) + B𝐶̅ 𝐷
̅ ̅ ̅ ̅ ̅̅̅̅̅̅̅̅̅̅̅̅
̅ = 𝐵̅(C + D) + B(𝐶 + 𝐷)
W = A + BC + BD = A + B(C + D)
Logic diagram:

Figure 3.35: Implementation of BCD to Xcess-3 Code Convertor

3.9.4 Xcess-3 to BCD Code
The process of converting Xcess-3 TO BCD Code is opposite to the process of converting BCD to
Xcess-3.
BCD code can be calculated by subtracting 3, i, e., 0011 from each digit Xcess-3 code.
Let W, X, Y, and Z are the bits representing the binary numbers, where Z is the LSB and W is the
MSB, and Let A, B, C, and D are the bits representing the Xcess-3 code of the binary numbers,
where D is the LSB and A is the MSB. The truth table for the conversion is given below. The X’s
mark is don’t care condition.

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Truth table:
Table 3.20: Truth Table of an Xcess-3 to BCD
Input Xcess-3 Output BCD
A B C D W X Y Z
0 0 0 0 x x x x
0 0 0 1 x x x x
0 0 1 0 x x x x
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

K-Map Simplification:

Corresponding minimized Boolean expressions for Xcess-3 code bits:

W = AB+ACD
X = 𝐵̅ 𝐶̅ + 𝐵̅ 𝐷
̅ + BCD
Y = 𝐶̅ D+C 𝐷 ̅
Z=𝐷 ̅

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Logic diagram:

Figure 3.36: Implementation of Xcess-3 to BCD Code Convertor

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