UNIT II 8086 SYSTEM BUS STRUCTURE

Pin Diagram of 8086 Processor:

The 8086 signals can be categorized in three groups. The first are the signals
having common functions in minimum as well as maximum mode, the second are the
signals which have special functions in minimum mode and third are the signals having
special functions for maximum mode

AD15-AD0: These are the time multiplexed memory I/O address and data lines.
When ALE = 1 :AD15-AD0 contains the address
ALE = 0 :AD15-AD0 contains the data

A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address and status lines.
During T1, these are the most significant address lines or memory operations. The address
bits are separated from the status bits using latches controlled by the ALE signal.

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 S4 S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

BHE/S7-Bus High Enable/Status: The bus high enable signal is used to indicate the transfer
of data over the higher order (D15-D8) data bus. It goes low for the data transfers over D15-
D8 and is used to derive chip selects of odd address memory bank or peripherals.
One bank is connected to the lower half of the 16-bit data bus (D0 – D7) and
contains even address bytes. i.e., when A0 bit is low, the bank is selected. The other
bank is connected to the upper half of the data bus (D8 - D15) and contains odd
address bytes. i.e., when A0 is high and BHE (Bus High Enable) is low, the odd bank
is selected. A specific byte within each bank is selected by address lines A1-A19.

RD-Read: Read signal, when low, indicates the peripherals that the processor is
performing a memory or I/O read operation.

READY: This is the acknowledgement from the slow devices or memory that they have
completed the data transfer. The signal made available by the devices is synchronized by the
8284A clock generator to provide ready input to the 8086. The signal is active high.

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 BHE A0 Indication
0 0 Whole Word
0 1 Upper byte from or to odd address
1 0 Upper byte from or to even address
1 1 No Operation

INTR : Interrupt Request: If any interrupt request is pending, the processor enters
the interrupt acknowledge cycle. This can be internally masked by resetting the
interrupt enable flag. This signal is active high and internally synchronized.

TEST: This input is examined by a 'WAIT' instruction. If the TEST input goes low,
execution will continue, else, the processor remains in an idle state.

NMI: Non-maskable Interrupt: This is an edge-triggered input which causes a Type

2 interrupt. The NMI is not maskable internally by software.

RESET: This input causes the processor to terminate the current activity and start execution
from FFFF0H. The signal is active high and must be active for at least four clock cycles. It
restarts execution when the RESET returns low. RESET is also internally synchronized.

CLK : The clock input provides the basic timing for processor operation and bus control
activity. The range of frequency for different 8086 versions is from 5MHz to 10MHz.

VCC :+5V power supply for the operation of the internal circuit. GND ground for the
internal circuit.

MN/MX: The logic level at this pin decides whether the processor is to operate in either
minimum (single processor) or maximum (multiprocessor) mode.
The following pin functions are for the minimum mode operation of 8086.

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 M/IO: Memory/IO: When it is low, it indicates the CPU is having an I/O operation, and
when it is high, it indicates that the CPU is having a memory operation.

INTA: Interrupt Acknowledge:. It means that the processor has accepted the interrupt.

ALE: Address latch Enable: This output signal indicates the availability of the valid
address on the address/data lines, and is connected to latch enable input of latches.

DT/R Data Transmit/Receive: This output is used to decide the direction of data
flow through the transceivers (bidirectional buffers). When the processor sends out
data, this signal is high and when the processor is receiving data, this signal is low.

DEN: Data Enable This signal indicates the availability of valid data over the
address/data lines. It is used to enable the transceivers (bidirectional buffers) to
separate the data from the multiplexed address/data signal.

HOLD, HLDA-Hold/Hold Acknowledge: When the HOLD line goes high, it indicates
to the processor that another master is requesting the bus access. The processor,
after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin.
At the same time, the processor floats the local bus and control lines. When the
processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an
asynchronous input, and it should be externally synchronized.

The following pin functions are applicable for maximum mode operation of 8086.

LOCK: This output pin indicates that other system bus masters will be prevented from
gaining the system bus, while the LOCK signal is low. When the CPU is executing a
critical instruction which requires the system bus, the LOCK prefix instruction ensures
that other processors connected in the system will not gain the control of the bus. The
8086, while executing the prefixed instruction, asserts the bus lock signal output, which
may be connected to an external bus controller.

QS1, QS0-Queue Status: These lines give information about the status of
the code-prefetch queue.

QS1 QS1 Characteristics

0 0 No operation

0 1 First byte of opcode from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

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 S2,S1,S0: Status Lines: These are the status lines which reflect the type of operation,
being carried out by the processor. These status lines are encoded in table.

S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive State

RQ/GT0, RQ/GT1: ReQuest/Grant :These pins are used by other local bus masters, in
maximum mode, to force the processor to release the local bus at the end of the processor's
current bus cycle. Each of the pins is bidirectional with RQ/GT0 having higher priority
than RQ/ GT1, RQ/GT pins have internal pull-up resistors and may be left unconnected.

Ttiming diagram of write cycle in 8086 in minimum mode.

In a minimum mode 8086 system, the microprocessor 8086 is operated in

minimum mode by strapping its MN/MX* pin to logic1. In this mode, all the control
signals are given out by the microprocessor chip itself. There is a single
microprocessor in the minimum mode system. The remaining components in the
system are latches, transceivers, clock generator, memory and I/O devices.
The latches are generally buffered output D-type flip-flops, 8282. They are
used for separating the valid address from the multiplexed address/data signals and
are controlled by the 8-bit ALE signal generated by 8086.
Transceivers are the bidirectional buffers. They are required to separate the valid data
from the time multiplexed address/data signal. They are controlled by two signals, namely,
DEN* and DT/R*. The DEN* signal indicates that the valid data is available on the

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 data bus, while DT/R indicates the direction of data, i.e. from or to the processor.

The system contains memory for the monitor and users program storage.
Usually, EPROMS are used for monitor storage, while RAMs for users program
storage. A system may contain I/O devices for communication with the processor as
well as some special purpose I/O devices.
The clock generator generates the clock from the crystal oscillator and then shapes it and
divides to make it more precise so that it can be used as an accurate timing reference for the
system. The clock generator also synchronizes some external signals with the system clock. Since
it has 20 address lines and 16 data lines, the 8086 CPU requires three octal address latches and
two octal data buffers for the complete address and data separation.
The working of the minimum mode configuration system is described in terms
of the timing diagrams. The opcode fetch and read cycles are similar. Hence the
timing diagram can be categorized into two parts, the first is the timing diagram for
read cycle and the second is the timing diagram for write cycle.

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 Timing Diagram for Read Cycle

The above figure shows the timing diagram of read cycle. The read cycle begins in T 1 with the
assertion of the address latch enable (ALE) signal and also M/IO* signal. During the negative
going edge of this signal, the valid address is latched on the local bus. The BHE*
and A0 signals address low, high or both bytes. From T l to T4, the M/IO* signal
indicates a memory or I/O operation. At T2 the address is removed from the local
bus and is sent to the output. The bus is then tristated. The read (RD*) control signal
is also activated in T2 .The read (RD) signal causes the addressed device to enable
its data bus drivers. After RD* goes low, the valid data is available on the data bus.
The addressed device will drive the READY line high, when the processor returns the
read signal to high level, the addressed device will again tristate its bus drivers.

Timing Diagram for Write Cycle

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 Figure shows the timing diagram of write cycle. A write cycle also begins with the assertion
of ALE and the emission of the address. The M/IO* signal is again asserted to indicate a
memory or I/O operation. In T2 after sending the address in Tl the processor sends the data
to be written to the addressed location. The data remains on the bus until middle of T 4 state.
The WR* becomes active at the beginning ofT2 (unlike RD* is somewhat delayed in T2 to
provide time for floating). The BHE* and A0 signals are used to select the proper byte
or bytes of memory or I/O word to be read or written. The M/IO*, RD* and WR* signals
indicate the types of data transfer as specified in Table

M/IO RD WR Transfer Type

0 0 1 I/O read

0 1 0 I/O write

1 0 1 Memory read

1 1 0 Memory write

Maximum mode configuration of 8086:

*
In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
* * *
In this mode, the processor derives the status signals S 2 , S1 and S0 . Another chip
called bus controller derives the control signals using this status information. In the
maximum mode, there may be more than one microprocessor in the system
configuration. The other components in the system are the same as in the minimum
mode system. The general system organization is as shown in the figure
The basic functions of the bus controller chip IC8288, is to derive control signals like
RD* and WR* (for memory and I/O devices), DEN*, DT/R*, ALE, etc. using the information
made available by the processor on the status lines. The bus controller chip has
input lines S2*, S1* and S0* and CLK. These inputs to 8288 are driven by the CPU. It derives
the outputs ALE, DEN*, DT/R*, MWTC*, AMWC*, IORC*, IOWC* and AIOWC*. IORC*, IOWC*
are I/O read command and I/O write command signals respectively. These signals enable an
IO interface to read or write the data from or to the addressed port. The MRDC*, MWTC* are
memory read command and memory write command signals respectively and may be used
as memory read and write signals. All these command signals instruct the memory to accept
or send data from or to the bus. For both of these write command signals, the advanced signals
namely AIOWC* and AMWTC* are available. They also serve the same purpose, but are
activated one clock cycle earlier than the IOWC* and

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 MWTC* signals, respectively.

The maximum mode system timing diagrams are also divided in two portions as read
(input) and write (output) timing diagrams. The address/data and address/status timings are
similar to the minimum mode. ALE is asserted in T 1, just like minimum mode. The only
difference lies in the status signals used and the available control and advanced
command signals.

Memory Write Timing in Maximum Mode

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 Memory Read Timing in Maximum Mode

Multiprocessor configuration:

MULTIPROCESSOR SYSTEMS
A multiprocessor system will have two or more processors that can execute
instructions or perform operations simultaneously.

Need for Multiprocessor Systems :

Due to limited data width and lack of floating point arithmetic instructions,
8086requires many instructions for computing even single floating point operation. For
this Numeric Data Processor (8087) can help 8086 processor.

Advantages :
f. Several low cost processors may be combined to fit the needs of an application
while avoiding the expense of the unneeded capabilities of a centralized system.
2. It is easy to add more processor for expansion as per requirement.
3. When a failure occurs, it is easier to replace the faulty processor.
4. In a multiprocessor system implementation of modular processing of task can be achieved

Maximum mode of 8086 is designed to implement 3 basic multiprocessor configurations:

1. Coprocessor (8087)
2. Closely Coupled (8089)
3. Loosely Coupled (Multibus)

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 Coprocessor Configuration
In coprocessor configuration both the CPU (8086) and external processor (Math
Coprocessor8087) share entire memory and I/O sub system. They also share same
bus control logic and clock generator.8086 is the master and 8087 is the slave.
An instruction to be executed by the coprocessor is indicated by an escape(ESC)
prefix or instruction.
1. The 8086 fetches the instructions.
2. The coprocessor monitors the instruction sequence and captures its own instructions.

3. The ESC is decoded by the CPU and coprocessor simultaneously.

4. The CPU computes the 20 bit address of memory operand and does adummy
read. The coprocessor captures the address of the data and obtains control of
the bus to load or store as needed.
5. The coprocessor sends BUSY (high) to the TEST pin.
6. The CPU goes to the next instruction and if this is an 8086 instruction, the
CPU and coprocessor execute in parallel.
7. If another coprocessor instruction occurs the 8086mustwait until BUSY goes
low ie, TEST pin become active. To implement this, a WAIT instruction is put in
front of most 8087instructionsby the Assembler.
8. The WAIT instruction does the operations ie , wait until the TEST pin is active.
9. The coprocessor also makes use of Queue Status (QS0-QS1)of the 8086
Instructions queue

Closely Coupled Configuration

Coprocessor and closely coupled configuration are similar in that both the
8086 and the external processor (8089) share:

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  Memory
 I/O system
 Bus and Bus control logic
 Clock generator
The interaction between 8086 and coprocessor or independent processor is shown below

The main difference between coprocessor and closely coupled configuration is, no special
instruction WAIT or ESC is used. The communication between 8086 and independent
processor is done through memory space. As shown in Figure the 8086 sets up a message
in memory and wakes up independent processor by sending command to one of its ports. The
independent processor then accesses the memory to execute the task in parallel with the
8086. When task is completed the external processor informs the 8086 about the completion
of task by using either a status bit or an interrupt request

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 Loosely Coupled Configuration:
In loosely coupled configuration a number of modules of 8086 can be interfaced
through a common system bus to work as a multiprocessor system. Each module is
an independent microprocessor based system with its own clock source, and its own
memory and I/O devices interfaced through a local bus. Each module can also be a
closely coupled configuration of a processor or coprocessor The block diagram of a
loosely coupled configuration of 8086 is shown in figure

Advantages
 High system throughput can be achieved by having more than one CPU.
 The system can be expanded in modular form. Each bus master module is an
independent unit and normally resides on a separate PC board. One can be added or
removed without affecting the others in the system.
 A failure in one module normally does not affect the breakdown of the entire system
and the faulty module can be easily detected and replaced
 Each bus master has its own local bus to access dedicated memory or IO
devices so a greater degree of parallel processing can be achieved

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 Bus arbitration problem in multiprocessors:

Multiple devices may need to use the bus at the same time so it must have a way
to arbitrate multiple requests. Bus arbitration schemes usually try to balance:

 Bus priority – the highest priority device should b e serviced first

 Fairness – even the lowest priority device should n ever be completely locked
out from the bus
Bus arbitration schemes can be divided into
three classes [Link] chaining.
2. Polling.
3. Independent requesting.

Daisy Chaining
In Daisy Chaining method all masters make use of the same line for bus
request. In response to a bus request, the controller sends a bus grant if the bus is
free. The bus grant signal serially propagates through each master until it encounters
the first one that is requesting access to the bus. This master blocks the propagation
of the bus grant signal, activates the busy line and gains control of the bus. Therefore
any other requesting module will not receive the grant signal and hence cannot get
the bus access. This bus allocation scheme is simple and cheaper But failure of any
one master causes the whole system to fail and arbitration is slow due to the
propagation delay of bus grant signal is proportional to the number of masters

Polling
In polling method, the controller sends address of device to grant bus access.
The number of address lines required is depend on the number of masters connected
in the system. For example, if 3

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 masters are connected in the system, one address line is required. In response to a bus
request, controller generates a sequence of master addresses When the requesting
master recognizes the address, it activates the busy line and begins to use the bus. The
priority can be changed by altering the polling sequence stored in the controller Another
one advantage of this method is, if one module fails entire system does not fail.

Independent Priority

In the independent priority scheme each master has a separate pair of bus
request (BRQ) and bus grant (BGR) lines and each pair has a priority assigned to it.
The built in priority decoder within the controller selects the highest priority request
and asserts the corresponding bus grant signal. Synchronization of clocks must be
performed once a master is recognized, Master will receive a common clock from
one side and pass it to the controller which will derive a clock for transfer. Due to
separate pairs of bus request and bus grant signals, arbitration is fast.

1. Define bus. Why bus request and cycle stealing are required.
The microprocessors functions as the CPU in the stored program model of
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 the digital computer. Its job is to generate all system timing signals and synchronize the
transfer of data between memory, I/O, and itself. It accomplishes this task via the three-
bus system architecture named as address bus, data bus and control bus.
The cycle stealing mode is used in systems in which the CPU should not be
disabled for the length of time needed for burst transfer modes. In the cycle stealing mode,
the DMA controller obtains access to the system bus the same way as in burst mode,
using BR (Bus Request) and BG (Bus Grant) signals, which are the two signals
controlling the interface between the CPU and the DMA controller. However, in cycle
stealing mode, after one byte of data transfer, the control of the system bus is deserted to
the CPU via BG. It is then continually requested again via BR, transferring one byte ofdata
per request, until the entire block of data has been transferred.

2. What are the advantages of coprocessor?

 A coprocessor is a special set of circuit in a microprocessor chip that is designed to
manipulate numbers or perform some other specialized function more quickly than the
basic microprocessor circuits could perform the same task.
 The coprocessor, also known as a math coprocessor, numeric coprocessor, or
floating- point unit ( FPU), became a physical part of the microprocessor chip.
Some coprocessors are still available as separate chips or circuit cards. These
are designed for specific applications such as high-end graphics, broadband
signal processing , and encryption / decryption .
 Coprocessors of this type make it possible to customize the various models in
a line of personal or business computers.

3. What are the significance of Bus High Enable Signal?

During T1 state the BHE should be used to enable data onto the most significant
half of the data bus, pins D15 - D8. Eight-bit oriented devices tied to the upper half of the
bus would normally use BHE to control chip select functions. BHE is Low during T1 state
of read, write and interrupt acknowledge cycles when a byte is to be transferred on the
high portion of the bus. The S7 status information is available during T2, T3 and T4 states.
The signal is active Low and floats to 3-state during "hold" state. This pin is Low during T1
state for the first interrupt acknowledge cycle.

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 4. What is meant by a loosely coupled configuration?
Aloosely coupled configuration provides the following advantages:
 High system throughput can be achieved by having more than one CPU.

 The system can be expanded in a modular form. Each bus master module is an
independent unit and normally resides on a separate PC board. Therefore, a bus
master module can be added or removed without affecting the other modules in the
system.
 A failure in one module normally does not cause a breakdown of the entire system
and the faulty module can be easily detected and replaced.
 Each bus master may have a local bus to access dedicated memory or I/O
devices so that a greater degree of parallel processing can be achieved. More
than one bus master module may have access to the shared system bus.

5. what is multiprogramming?
Two or more processes code is stored in memory at the same time and
is executed in a time multiplexed manner that system is called as
multiprogramming.

6. List the advanced microprocessors.

80286, 80386, 80486

Coprocessor cannot take control of the bus, it does everything through the CPU.
7. Justify the need for coprocessor.

 When the CPU executes the ESC instruction, the processor accesses the
memory operand by placing the address on the address bus. If a coprocessor
is configured to share the system bus, it will recognize the ESC instruction
and therefore will get the opcode and the operand.

8. How many memory locations can be addressed by 8086

microprocessor?
20
It has a 20-bit address bus can access upto 2 memory locations (1 MB)
9. In what ways are the standard microprocessor and coprocessor differ from
each other?
The processor takes care of all the major processing and the co-processor or the
auxiliary processor unit takes care of some other things like arithmetic calculations or
graphics to allow the main processor to work on more difficult tasks.
A co-processor is a unique set of circuit. It is used in enhancing the functions of
the primary processor. It is intended to direct the performance and the functions of the
microprocessor. It has a quick performance than the primary processor.

10. How does the main processor distinguish its instructions from the co-processor
instructions when it fetches the instructions from memory?
ESC instruction is used to differentiate the processor and co-processor instruction
when it fetches the instruction from memory.

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 11. Compare Closely Coupled configuration with Loosely
Coupled Configuration.

Closely Coupled Loosely Coupled

Contains multiple CPUs that are connected
at the bus level. These CPU may have These are based on multiple standalone
access to a central shared memory or may signal or dual processor interconnected via a
participate in a memory hierarchy with local high speed communication system
and shared memory
They perform better and are physically
Opposite to closely coupled.
smaller than loosely coupled system.
More expensive. Less Expensive.

The delay experienced is short, data rate is

Delay is large, data rate is low.
high, and number of bits transferred per
second is large.

12. What is the floating point coprocessor?

8086 processor do not have instruction set for performing floating point arithmetic
operations, but the combination of this processor with the coprocessor 8087
canperform any application which heavily involves floating point calculation,
suchcombination is called floating point coprocessor.

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