5.1.
Theory
Digital circuit design follows a structured hierarchy, moving step by step from high-level ideas
to physical implementation. The process begins with the system specification, which defines
what the circuit should do. Next comes logic synthesis, where the required functions are
expressed using logic gates. After that is the circuit design stage, where those gates are translated
into transistor-level circuits. Then, in the physical design (layout) phase, transistors and their
interconnections are arranged on silicon. Finally, the design proceeds to manufacturing, where
the actual chip is produced. Each stage is crucial, since mistakes at any point can lead to circuit
failure or poor performance. Careful verification at every level ensures that the design meets
goals for speed, power, and chip area.
In this experiment, the objective was to design a 2-input AND gate using CMOS technology.
Instead of directly implementing the AND gate, we used a common technique: first building a 2-
input NAND gate, then feeding its output into an inverter. This works because NAND and NOR
gates are universal gates, meaning any logic function can be implemented using just them. This
method is often more efficient, requiring fewer transistors and simplifying the layout compared
to designing an AND gate directly.
The CMOS realization relies on both NMOS and PMOS transistors, arranged in a
complementary way so that when one type is active, the other is inactive—minimizing power
consumption. In the NAND gate, NMOS transistors are placed in series, while PMOS transistors
are connected in parallel, ensuring the output goes low only when both inputs are high. The
inverter then uses one NMOS and one PMOS to flip this output, producing the correct AND
logic. This stacked-transistor arrangement not only guarantees proper logical behavior but also
helps keep the circuit compact and power-efficient.
A 2-input AND gate can be implemented hierarchically using a 2-input NAND gate followed by
an inverter. The NAND gate produces the output:
𝑌 = (𝐴. 𝐵)′
and when this output is passed through an inverter, the result becomes:
𝑌′ = (𝐴. 𝐵)
Fig. 5.1: simple diagram of inverter and AND gate
5.2 Schematic Diagrams:
We have already created symbol of NAND Gate and NOT gate . These are use as a building block and
created a AND gate by cascading a NAND and Inverter.
Fig. 5.2: Schematic Diagram of AND Gate
Symbol Of AND Gate:
Now we have created the symbol for the AND Gate.
Figure 5.3: Symbol of AND Gate
Input and Output Waveform:
Layout Design:
We have used the previously created NAND and Inverter as a instance now, and the appear like the
below:
5.5. Final Design Layout:
Now we have connected the circuit and the final layout is shown in Figure 5.5.
Fig. 5.5: Final Design Layout of AND Gate.
