VLSI Design Flow: RTL To GDS (NPTEL Course)

Solution of numerical problem for Week 6

2. The Boolean function: 𝑓(𝑥1 , 𝑥2 , 𝑥3 ) = (𝑥1 +𝑥2 )(𝑥1 ′+𝑥2 ′)(𝑥1 + 𝑥3 ) is satisfiable for:
a) It is not satisfiable
b) 𝑥1 = 1, 𝑥2 = 1, 𝑥3 = 1
c) 𝑥1 = 0, 𝑥2 = 1, 𝑥3 = 0
d) 𝑥1 = 1, 𝑥2 = 0, 𝑥3 = 1
Solution:

The given function is in the CNF form.

We have to check the value of 𝑓(𝑥1 , 𝑥2 , 𝑥3 ) by putting the values of 𝑥1 , 𝑥2 , 𝑥3
If the value of 𝑓(𝑥1 , 𝑥2 , 𝑥3 ) is 1 then the function is satisfiable otherwise the function is
not satisfiable.

For option 𝑏) 𝑥1 = 1, 𝑥2 = 1, 𝑥3 = 1 , 𝑓(𝑥1 , 𝑥2 , 𝑥3 ) = 0; hence not satisfiable.

For option 𝑐) 𝑥1 = 0, 𝑥2 = 1, 𝑥3 = 0 , 𝑓(𝑥1 , 𝑥2 , 𝑥3 ) = 0; hence not satisfiable.
For option d) 𝑥1 = 1, 𝑥2 = 0, 𝑥3 = 1 , 𝑓(𝑥1 , 𝑥2 , 𝑥3 ) = 1; hence satisfiable.
Hence the correct option (d).

5. Consider an FSM with five states 𝑄 = {𝑠0 , 𝑠1 , 𝑠2 , 𝑠3 , 𝑠4 }. The states are represented by
3 state bits {𝑥2 𝑥1 𝑥0 }. Assume that these states {𝑠0 , 𝑠1 , 𝑠2 , 𝑠3 , 𝑠4 } are encoded as
{000,001,010,011,100}. In this representation, the characteristics function 𝑓(𝑥2 , 𝑥1 , 𝑥0 )
representing the subset of states: 𝐴 = {𝑠1 , 𝑠2 , 𝑠4 } is:
a) 𝑥2 ′𝑥1 ′𝑥0 ′ + 𝑥2 ′𝑥1 𝑥0 ′+𝑥2 𝑥1 ′𝑥0 ′
b) 𝑥2 ′𝑥1 ′𝑥0 + 𝑥2 ′𝑥1 𝑥0 +𝑥2 𝑥1 ′𝑥0 ′
c) 𝑥2 ′𝑥1 ′𝑥0 ′ + 𝑥2 ′𝑥1 𝑥0 +𝑥2 𝑥1 ′𝑥0 ′
d) 𝑥2 ′𝑥1 ′𝑥0 + 𝑥2 ′𝑥1 𝑥0 ′+𝑥2 𝑥1 ′𝑥0 ′
Solution:
We have encoded the states as
𝑠0 can be written as 𝑥2 ′𝑥1 ′𝑥0 ′
𝑠1 can be written as 𝑥2 ′𝑥1 ′𝑥0
𝑠2 can be written as 𝑥2 ′𝑥1 𝑥0 ′
𝑠3 can be written as 𝑥2 ′𝑥1 𝑥0 and so on
The characteristic function of the set of states of 𝐴 = {𝑠1 , 𝑠2 , 𝑠4 } can be written as:
𝑓(𝑥2 , 𝑥1 , 𝑥0 ) = 𝑥2 ′𝑥1 ′𝑥0 + 𝑥2 ′𝑥1 𝑥0 ′+𝑥2 𝑥1 ′𝑥0 ′
Each minterm corresponds to one state. Hence the correct option is (d).
 VLSI Design Flow: RTL To GDS (NPTEL Course)

Solution of numerical problem for Week 7

3. Consider the AND gate shown below:

The delay and the output slew of different arcs are shown below:

Arc Delay (ps) Output Slew at pin Z (ps)

A→Z 12 12
B→Z 15 5
C→Z 30 8

The arrival time at different input pins are as follows:

Pin Arrival Time (ps)

A 15

B 25

C 5

When graph-based analysis (GBA) is performed for the setup or late mode check, what will
the arrival time and output slew be at pin Z?

Solution:

Arrival time from A to Z= Arrival time at pin A + Delay of Arc A →Z= 15+12=27 ps
Arrival time from B to Z=Arrival time at pin B + Delay of Arc B →Z=25+15=40 ps
Arrival time from C to Z=Arrival time at pin C + Delay of Arc C →Z=5+30=35 ps

For setup or late check, the maximum arrival time should be taken.
Hence, arrival time at Z = 40 ps

For GBA, the maximum slew from any path is taken. The maximum slew is from A → Z. Its
value is 12 ps.
Hence, the correct answer is (e) Arrival Time = 40 ps Output Slew = 12 ps

4. For PBA, for the B to Z path:

Arrival time = Arrival time at pin B + Delay of Arc B →Z= 25+15=40 ps
For the PBA case we take the arrival time and slew from the same path.
Slew = 5 ps.
 Hence, the correct answer is (b) Arrival Time = 40 ps and Output Slew = 5 ps

5. For the same question above (i.e., Q-3), what will be the arrival time and the output slew at the
pin Z when graph-based Analysis (GBA) is performed for the hold check or early mode check at pin
Z?
Solution:

Arrival time from A to Z= Arrival time at pin A + Delay of Arc A→Z= 15+12=27 ps
Arrival time from B to Z=Arrival time at pin B + Delay of Arc B→Z=25+15=40 ps
Arrival time from C to Z=Arrival time at pin C + Delay of Arc C→Z=5+30=35 ps

For hold or early check, the minimum arrival time should be taken.
Hence, arrival time at Z = 27 ps

For GBA, in the hold check, the minimum slew from any path is taken.
The minimum slew is from B to Z. Its value is 5 ps.
Hence, the correct answer is (d) Arrival Time = 27 ps Output Slew = 5 ps

6. Consider the following synchronous circuit.

The following attributes are valid for the flip-flops FF1 and FF2: setup time=30 ps, hold
time=20 ps, and CLK-to-Q delay=45 ps. The delay of each inverter is 80 ps. Ignore the wire
delay.

Assume that the clock period is 1000 ps. What is the setup slack at the timing end-point
FF2/D?

Solution:
Here the launch flip flop is FF1 and the capture flip flop is FF2.
Here, Tcapture=Tlaunch=0 ps [Since, delay on clock path is only the wire delay, which must be
ignored, according to the question]

Arrival time at FF2/D (AT) = CLK-to-Q delay of FF1 + delay of inverter G2 = 45 + 80 = 125 ps
Required time (RT) = Clock period – setup time of FF2 = 1000 – 30ps = 970 ps
Setup Slack = Required time – Arrival time = 970-125= 845 ps
Hence, correct answer is (f) 845 ps

7. For the same question above, what is the hold slack at the timing end-point FF2/D?
Arrival time at FF2/D (AT) = CLK-to-Q delay of FF1 + delay of inverter G2 = 45 + 80 = 125 ps
Required time (RT)= hold time of FF2=20 ps
Hold Slack = Arrival time – Required time = 125 - 20=105 ps.
Hence, the correct answer is (e) 105 ps.
 VLSI Design Flow: RTL To GDS (NPTEL Course)

Solution of numerical problem for Week 8

6. Consider the following synchronous circuit.

The following attributes are valid for the flip-flops FF1 and FF2: setup time=50 ps, hold
time=20 ps, and CLK-to-Q delay=60 ps. The delay of each inverter is 80 ps. Ignore the wire
delay.
Assume that we have defined the following constraints in the SDC file (all time units are in
picoseconds):

create_clock -name CLK -period 800 [get_ports CLK]

set_input_delay -clock [get_clocks CLK] 120 [get_ports A]
set_output_delay -clock [get_clocks CLK] 200 [get_ports Z]

What is the setup slack at the timing end-point FF1/D?

a. 750 ps
b. 720 ps
c. 700 ps
d. 680 ps
e. 600 ps
f. 550 ps
g. 500 ps

Solution:
From the snapshot of the given constraint file, we can infer the following.
Clock period = 800 ps [from the command create_clock]
Arrival time at FF1/D=120 [i.e., from set_input_delay command] + 80 [i.e., delay of
inverter G1] = 200 ps
Required time = Clock period – setup time of FF1 = 800 – 50 ps = 750 ps
Setup slack = Required time – Arrival time = 750 - 200 = 550 ps

Hence, option (f) 550 ps is correct.

7. For the question above, what is the hold slack at the timing end-point FF1/D?
a. 200 ps
b. 190 ps
 c. 180 ps
d. 0 ps
e. -180 ps
f. -190 ps
g. -200 p

Solution:
Arrival time at FF1/D=120 [i.e., from set_input_delay command] + 80 [i.e., delay of
inverter G1] = 200 ps
Required time = hold time of FF1 =20 ps
Hold slack = Arrival time - Required time = 200-20 = 180 ps

Hence, option (c) 180 ps is correct.

8. For the question above, what is the setup slack at the timing end-point port Z?
a. 600 ps
b. 550 ps
c. 480 ps
d. 460 ps
e. 400 ps
f. 360 ps
g. 300 ps

Solution:
Clock period = 800 ps [from the command create_clock]
Arrival time at Z = 60 [i.e., CLK-to-Q delay of FF2] + 80 [i.e., delay of inverter G3] =
140 ps
Required time at Z = Clock period – output-delay specified at Z [i.e., from
set_output_delay command] = 800 –200 ps = 600ps
Setup slack = Required time – Arrival time = 600 - 140 = 460 ps

Hence, option (d) 460 ps is correct.

 VLSI Design Flow: RTL To GDS (NPTEL Course)

Solution of numerical problem for Week 9

2. Assume that an inverter drives a load capacitance of 0.2 ff and the supply voltage is 1 V. Further
assume that the inverter makes 1 × 109 ZERO-to-ONE transitions in 1 second and 1 × 109 ONE-to-ZERO
transitions in 1 second. What is the power dissipated in charging and discharging the load capacitance?
a. 1 × 10−7 W
b. 2 × 10−7 W
c. 5 × 10−8 W
d. 1 × 10−8 W

Solution:
Energy dissipated in one 0→1 and 1→0 transition = CV2
= 0.2×10-15×(1)2 = 2×10-16 J
No. of transition 0→1 and 1→0 per second = 1 × 109
Power dissipated in the 0→1 transitions = Energy per complete transition (i.e., 0→1 and 1→0) ×
Number of transitions per second
= 2×10-16× 1 × 109 = 2 × 10−7W

Hence, option (b) 2 × 10−7 W is correct.

5. Consider a five-input NAND gate. How many single stuck-at faults are possible for this NAND gate?
a. 5
b. 6
c. 10
d. 12
Solution:

There are 5 inputs and 1 output so there are 6 total fault sites possible.
At a single fault site there are 2 faults possible.
1) Stuck-at-0
2) Stuck-at-1
So total 12 = (6×2) faults are possible. Hence, option (d) 12 is correct

6. What is the minimum number of test vectors for the five-input NAND gate that can detect ALL
possible single stuck-at faults?
a. 5
b. 6
c. 7
d. 8
Solution:
Here A, B, C, D, E are inputs and Z is the output of the NAND gate.
 Faults Site Test Vector

SA0 at A, B, C, D, E. 11111
SA1 at Z

SA1 at A. 01111
SA0 at Z

SA1 at B. 10111
SA0 at Z

SA1 at C. 11011
SA0 at Z

SA1 at D. 11101
SA0 at Z

SA1 at E. 11110
SA0 at Z

Hence, option (b) 6 is correct.

 VLSI Design Flow: RTL To GDS (NPTEL Course)

Solution of numerical problem for Week 10

2. For the circuit shown below, the test pattern to detect SA1 at G3/Y is:

a. A=1 B=1 C=1 D=0

b. A=1 B=0 C=0 D=1
c. A=1 B=1 C=0 D=1
d. A=0 B=0 C=1 D=0

Solution:
Fault Activation: To activate a SA1 fault, a value of 0 (opposite of the fault value) must be
obtained at G3/Y. This can be done by any of the following combinations:
A=0, B=1, C=1
A=1, B=0, C=1
A=1, B=1, C=1

Fault Propagation: The fault needs to be propagated to the output. We have to make side input
of G4 non-controlling (i.e. G4/X2 should be 0).

Line Justification: Line justification needs to be done such that G4/X2=0.

To obtain G4/X2=0, we must have G2/Y=0, which can further be obtained using:
C=0, D=0
C=1, D=0
C=0, D=1.
However, from fault activation, we must have C=1.
Hence, only C=1, D=0, is possible from the above combinations.
So, following test patterns can detect the above fault:
A=0, B=1, C=1, D=0
A=1, B=0, C=1, D=0
A=1, B=1, C=1, D=0
From the given options in the question, only (a) matches.
Hence the answer is (a) A=1 B=1 C=1 D=0