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6 Architecture Gate

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ANIK CHAKRABORTY
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18 views146 pages

6 Architecture Gate

Uploaded by

ANIK CHAKRABORTY
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

INSTRUCTION EXECUTION

INSTRUCTION FORMAT
INSTRUCTION SET
ADDRESSING MODES
From 0 upto 255 modulo 256 is well 0 upto 255 so, block 0 can be placed in block 0,block 1
can be placed in block 1 ,…,block 255 can be placed in block 255 and that is written as 0->0,

255->255 etc. but then 256->0, 257->1 etc.

So we can see the main problem is all 256n blocks will all be mapped to 0, all 256n + 1 will
be mapped to 1 etc. So say you require both 0 and 256 then it will be a problem to
distinguish
In typical computer, we have more read operations than write . Hence we usually try to
make the common case(read operations) fast. But that doesn’t mean we ignore write
completely.
The interrupt can actually jump from anywhere in the program depending on where is the
case.
So En=0 means high impedance state, basically Output is electrically disconnected
So these switches will connect either CPU or DMA controller to the Memory. Under no
circumstances can CPU and DMA controller both get connected to the Memory. Only one of
them at a time. Otherwise there will be memory clash.

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