ASIC CONSTRUCTION

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LOW-LEVEL DESIGN ENTRY

the initial step in describing a microelectronic system for Electronic Design Automation (EDA) tools.
Traditionally, design entry involved creating a schematic - a picture illustrating component connections -
similar to an architect's blueprint.

The schematic shows how all the components are connected together,
the connectivity of an ASIC

The circuit schematic is a picture, an easy format for us to understand and use, but
computers need to work with an ASCII or binary version of the schematic that we call
a netlist.

The binary version of the schematic is called netlist.

The output of a schematic-entry tool is thus a netlist file that contains a description of all
the components in a design and their interconnections.

The schematic translates into a netlist, a computer-readable file listing components and their connections.
However, for programmable elements like ASICs, design entry might also involve writing code or specifying
memory content (PROM microcode).

 Schematic: This is a visual representation of the electronic circuit, similar to an architect's blueprint
for a building. It uses symbols to represent electronic components like resistors, transistors, and
integrated circuits (ICs). Lines connecting these symbols depict the electrical connections between
them. Schematics are easy for humans to understand and create, making them a popular choice for
design entry.

 Netlist: In contrast to the schematic, a netlist is a textual representation of the circuit's connectivity.
It's a list that describes all the components in the design and how they are interconnected. Think of it
like a table with columns for component names, pin numbers, and the "net" (electrical connection)
they are connected to. While not as intuitive for humans as a schematic, netlists are machine-
readable. EDA (electronic design automation) tools can understand and use this information to
perform tasks like circuit simulation or generating the physical layout of the circuit board.

With increasingly complex systems, alternative design entry methods are emerging, including Hardware
Description Languages (HDLs) that can directly generate netlists through logic synthesis. The choice of method
depends on the specific design, with the key objective being a complete system specification for both
functionality and understanding.

Design entry is thus an important part of documentation .

Until recently most ASIC design entry used schematic entry. As ASICs have become more
complex, other design-entry methods are becoming common. Alternative design-entry
methods can use graphical methods, such as a schematic, or text files, such as
a programming language. Using a hardware description language ( HDL ) for
design entry allows us to generate netlists directly using logic synthesis .
 Schematic Entry

 Schematic entry is a common method for designing ASICs.

 Schematic sheets are used to draw circuit schematics. Standard schematic sheet sizes include ANSI
A-E and ISO A4-A0.
 A frame or border is drawn around the schematic containing information like designer name, date and
list of modifications.
 Schematic-entry tools for ASIC design are similar to those for PCB design.
 A large ASIC contains hundreds of thousands of components, making it impractical to draw every
component on an ASIC schematic.
 IEEE-recommended dimensions and their construction for logic-gate symbols. (a) NAND
gate (b) exclusive-OR gate (an OR gate is a subset).

Figure 9.2 shows some pictorial definitions of objects you can use in a simple schematic.

Hierarchical Design

 Hierarchical design reduces complexity in schematics by breaking them down into levels.
 Similar to building plans, a top-level schematic shows the overall design, while lower levels show
details of smaller components.
 Subschematics (like office plans) are children of parent schematics (like floors).
 Hierarchical design is essential for managing complexity in large ASICs with thousands of logic gates.
 An alternative, flat design with everything on one schematic, is impractical for modern ASICs.
 An electrical schematic can contain subschematics. The subschematic, in turn, may
contain other subschematics. Figure 9.3 illustrates the principles of schematic
hierarchical design.
 FIGURE 9.3 Schematic example showing hierarchical design. (a) The schematic of a half-
adder, the subschematic of cell HADD. (b) A schematic symbol for the half adder. (c) A
schematic that uses the half-adder cell. (d) The hierarchy of cell HADD.
 The Cell Library

 ASIC schematic components come from a library of cells (modules, macros, books).
 There is no standard naming convention for cells across different vendors, making it difficult to switch
vendors after using their library.
 Cell behavior can also differ between vendors, causing problems when porting schematics.
 Most ASIC companies provide a schematic library of primitive gates to be used for
schematic entry.
 Primitive cells are basic logic gates like NAND gates.
 In hierarchical design, a cell can also be a more complex component like a flip-flop or even a
microprocessor.
 There are two types of macros for MGAs and programmable ASICs. hard macro & soft
macro
 The most common type of macro is a hard macro that includes placement information. A
hard macro can change in position and orientation, but the relative location of the
transistors, other layout, and wiring inside the macro is fixed.
 A soft macro contains only connection information (between transistors for a gate array
or between logic cells for a programmable ASIC). Thus the placement and wiring for a
soft macro can vary.
 The timing parameters for a soft macro can only be determined after you complete the
place-and-route step.
 Standard cells have layout information on all mask levels, while MGA hard macros only have info on
metal layers.
 An MGA hard macro contains layout information on just the metal, contact, and via
layers.
 An MGA soft macro or programmable ASIC macro does not contain any layout
information at all, just the details of connections to be made inside the macro.

Issues in cell library according to the passage

 Naming Inconsistency: There is no standard naming convention for cells across different
vendors. This makes it difficult to port schematics from one vendor to another.
  Behavioral Differences: Cells with the same function (e.g., MUX) can have different behavior
depending on the vendor. This can lead to bugs when porting schematics. It is know as
retargeting schematics, also known as porting a design.
 Lack of Standards: There are no universal standards for cell behavior and layout information,
making it difficult to switch between vendors.
 Soft Macros: Timing parameters for soft macros are unavailable until after place-and-route,
which can complicate the design process.

Names

 Cell vs Instance: A cell is the original design, while an instance is a specific placement of that cell
within a schematic.
 Naming: Each cell has a unique name, and each instance of that cell also has a unique instance
name.
 A cell instance is somewhere between a copy and a reference to a cell in a library.
 we represent each cell instance by a picture or icon , also known as a symbol
 Icon Confusion: The same icon can represent both a primitive cell (like a NAND gate) and a
subschematic (like a floor plan). There's no easy way to distinguish between the two on a schematic.
 Primitive Cell Definition: The definition of a primitive cell depends on the library. For schematic
designers, primitive cells are basic gates like NAND gates. For library designers, primitive cells are
transistors that make up the gates.

Schematic Icons and Symbols

 Subschematics and Subcells: A subschematic is a lower-level schematic that can be used as a

component within a higher-level schematic. Subcells are the cells within a subschematic.
 Derived Icons: Schematic tools can automatically create a derived icon (symbol) to represent a
subschematic in a higher-level schematic.
 Cell Hierarchy and Naming: Cells can contain other cells in a hierarchical manner. Subcells inherit
the name of the parent cell with a delimiter and their own instance name (e.g., L1.inv1). This helps
distinguish between identical subcells within a higher-level cell.
 Vectored Instances: A vectored instance represents multiple copies of a cell with a single symbol.
The cardinality specifies the number of copies (e.g., L[1:4] for 4 copies of cell L).
 Benefits of Hierarchy: Hierarchy reduces complexity in large schematics by allowing designers to
create reusable components.
 FIGURE 9.4 A cell and its subschematic. (a) A schematic library containing icons for the
primitive cells. (b) A subschematic for a cell, DLAT, showing the instance names for the
primitive cells. (c) A symbol for cell DLAT.
 Figure 9.4 (c) shows what a derived icon for a cell, DLAT.
 the instance name inv1 in the subschematic is a subcell (or submodule) of the cell DLAT.
the cell instance inv1 is a child of the cell DLAT , and cell DLAT is a parent of cell
instance inv1 .

a 4-bit latch:
 FIGURE 9.5 A 4-bit latch: (a) drawn as a flat schematic from gate-level primitives,
(b) drawn as four instances of the cell symbol DLAT, (c) drawn using a vectored instance
of the DLAT cell symbol with cardinality of 4, (d) drawn using a new cell symbol with cell
name FourBit.

Each primitive cell instance in this schematic must have a unique name.

1. Flat vs Hierarchical Design:

o Figure 9.5(a) shows a flat schematic with many primitive cells for a 4-bit latch. This can be tedious for
complex circuits.
o Hierarchical design uses subcells and instances to make things more manageable.
2. Using DLAT Cell:
o Figure 9.5(b) shows a hierarchical design where the 4-bit latch (FourBit) uses four instances of a
simpler DLAT cell. the different instance names: L1 , L2 , L3 , and L4
3. Vectored Instances:
o Figure 9.5(c) shows a vectored instance representing four copies of the DLAT cell. This reduces the
need for repetitive naming. Thus L[1:4] represents four instances: L[1] , L[2] , L[3] , L[4] .
o The cardinality of this instance is 4, meaning it has 4 copies.
4. Custom Symbol for 4-Bit Latch:
o Figure 9.5(d) shows a new symbol (FourBit) created specifically for the 4-bit latch. The symbol
for FourBit has a 4-bit-wide input bus for the four D inputs, and a 4-bit wide output bus
for the four Q outputs.
o This symbol has separate input and output buses for the latch.
5. Hierarchical Naming:
o Schematic tools use a special character to combine instance names hierarchically.
o This helps distinguish between subcells at different levels (e.g., L1.inv1, L2.inv1 for inverters within
DLAT instances).

Nets:

 Local vs. External Nets:

o Local nets connect components within a sub schematic (e.g., net n1 in Figure 9.4b).
o External nets connect to the outside world (e.g., D, EN, Q in schematic DLAT).
 Net Naming Challenge: When placing subcircuits with local nets (like n1) into a higher-level
schematic, nets with the same name might not be connected.
 Solution: Hierarchical Naming:
o A prefix is added to local net names to include the parent cell instance name and a delimiter
character (e.g., FourBit.L1:n1).
o The usual convention for naming nets in a hierarchical schematic uses the parent cell
instance name as a prefix to the local net name.
o A special character ( ':' '/' '$' '#' for example) that is not allowed to appear in names is
used as a delimiter to separate the net name from the cell instance name.
o This ensures unique names for nets even if they share the same local name within subcircuits.
 External Nets: Naming conventions for external nets connecting hierarchical blocks can vary
between schematic tools.
 Standardization in HDLs: Hardware Description Languages (VHDL, Verilog) have a standard way to
name nets in hierarchical structures.
 This naming is usually done automatically by the schematic-entry tool.
Example: FourBit .L1:n1 FourBit .L2:n1 FourBit .L3:n1 FourBit .L4:n1

The schematic DLAT also contains three external nets: D, EN, and Q . The terminals on
the symbol DLAT connect these nets to other nets in the hierarchical level above. For
example, the signal Trigger:flag in Figure 9.4 (c) is also Trigger.DLAT:Q .

Schematic Entry for ASICs and PCBs

A symbol on a schematic may represent a component, which may contain component
parts.

Reference Designators (For PCBs):

 Used in PCB design to uniquely identify components (e.g., resistors, ICs).

 Format: <prefix><number> (e.g., R99).
 Assigned during PCB routing to specific packages and parts within those packages.
 Example: IC "74174" (hex D flip-flop) might have multiple identical flip-flop parts inside. Assigning a
reference designator like "IC4" to the specific package on the PCB tells you where a particular flip-
flop is located (and its pin numbers).

Instance Names (For ASICs):

 In large hierarchical ASIC designs it is difficult to provide a unique reference designator
to each element. For this reason ASIC designs use instance names to identify the
individual components.
 Used in ASIC design to identify individual cells within a hierarchical design.
 More descriptive than reference designators, allowing for meaningful names.
 Meaningful names can be assigned to low-level components and also the symbols that
represent hierarchy.
 Created by joining cell names at different levels of hierarchy with a delimiter character (e.g., .).
 A special character is used as a delimiter and separates each level.
 Example: cpu.alu.adder.and01 identifies a specific AND gate within an adder unit of an ALU
block in a CPU.

Key Points:

 Reference designators are essential for PCB routing as they connect schematic symbols to physical
components on the board.
 Instance names are better suited for ASIC design due to their hierarchical nature and ability to
provide context within the design.

Connections

 Cell instances have terminals that are the inputs and outputs of the cell. Terminals are
also known as pins , connectors , or signals.
 The term pin reserve for the metal leads on an ASIC package. The term pin is used in
schematic entry and routing programs that are primarily intended for PCB design.
 Cell Terminals: These are the connection points of a cell, also called pins, connectors, or signals.
 Nets and Buses: Electrical connections are made with wires (nets). A group of related nets (e.g.,
address lines) can be bundled together into a bus.
 Electrical connections between cell instances use wire segments or nets
 Bundles vs Buses: If the signals are not closely related (e.g., data, control signals), use bundle or
array instead of bus.
 Breakouts/Rippers: Used to access individual nets within a bus (e.g., accessing specific bits from a
data bus).
 Swizzles: Some tools allow rearranging the order of bits within a bus (e.g., moving MSB to LSB).
This can be useful for operations like multiplying by 2 (shifting bits by one position).
FIGURE 9.6 An example of the use of a bus to simplify a schematic. (a) An address
decoder without using a bus. (b) A bus with bus rippers simplifies the schematic and
reduces the possibility of making a mistake in creating and reading the schematic.
 Vectored Instances and Buses

 16-Bit Latch Example: The 3 ways to create a 16-bit latch:

o Figure 9.7(a): Using 4 instances of a simpler 4-bit latch (FourBit).
o Figure 9.7(b): Creating a new symbol (SixteenBit) with separate 16-bit buses for data (D) and outputs
(Q). This is considered a good approach.
o Figure 9.7(c): Using a single vectored instance of FourBit with cardinality 4. This can lead to naming
issues.
 Bus Rippers and Naming Issues:
o The "bus rippers" which allow selecting specific bits from a bus (e.g., D1, D9-12).
o Using a vectored instance with bus rippers (Figure 9.7c) creates a situation where the bus width
doesn't match on either side of the ripper (e.g., D vs. D[9:12]). This can be confusing.
 Recommendation: it is recommends using the single-bus approach (Figure 9.7b) to avoid naming
problems with buses and rippers.
FIGURE 9.7 A 16-bit latch: (a) drawn as four instances of cell FourBit; (b)
drawn as a cell named SixteenBit; (c) drawn as four multiple instances of cell
FourBit.

Edit-in-Place

 Edit-in-Place:
o Allows editing a cell instance directly within the current schematic.
o Any changes made to the subcell instance propagate to all other instances of that same cell within
the design.
 Example: Office Building Analogy
o Imagine editing an "office floor" cell to change offices from "no window" to "window" type.
o Edit-in-place modifies all floors using that cell (floors 2-10).
 Instead of editing a cell in place, you may really want to edit just one instance of a cell
and leave any other instances unchanged. In this case you must create a new cell with a
new symbol and new, unique cell name. It might also be wise to change the instance
name of the new cell to avoid any confusion.
 Editing a Single Instance:
o If you only want to modify one instance (e.g., floor 3), you cannot use edit-in-place.
o Create a new cell with a unique name and symbol for that specific instance.
o Optionally, rename the instance itself (e.g., "FloorSpecial").
 Net Aliasing:
o Some tools allow aliasing nets to create a single name across the entire design hierarchy.
o This replaces local net names (e.g., D, Q in a flip-flop) with higher-level names (e.g., Clock1, Data2).
o This simplifies tracing signals throughout a complex design.

Attributes

 Elements to Name: You can assign names (or labels) to various schematic elements like
components, cell instances, nets, and terminals.
 You can also attach an attribute , or property , which describes some aspect of the
component, cell instance, net, or connector.
 Attributes: Additional descriptive properties (attributes) can be attached to these elements, some
with specific values.
 Each attribute has a name, and some attributes also have values.
 Naming Issues: Naming inconsistencies are a major challenge, particularly when sharing schematics
across different software tools.
 Cell Names and Filenames: Since cell information is often stored in databases, cell names often
correspond to filenames. This introduces specific naming considerations:
o Case sensitivity (uppercase vs lowercase matters)
o Avoiding name collisions (ensuring unique names)
o Handling special characters (spaces, underscores, foreign alphabets)
o First character restrictions (some systems may limit the first character)
o Name length limitations (e.g., 28 characters for NFS compatibility)

Netlist Screener

Error Checking with Schematic Netlist Screeners:

 These programs identify basic errors in schematics like:

o Unconnected cell inputs
o Unconnected cell outputs
o nets not driven by any cells,
o too many nets driven by one cell,
o nets driven by more than one cell.
 Screeners can run continuously during design or as a separate step.
 Designers may provide attributes to guide the checks.
 Screeners report errors with their locations for easy identification.
o Handles (like grid references) help pinpoint schematic elements.

The screener can work continuously as the designer is creating the schematic or can be
run as a separate program independently from schematic entry. Usually the designer
provides attributes that give the screener the information necessary to perform the
checks.

A screener usually generates a list of errors together with the locations of the problem
on the schematic where appropriate. Some editors associate an identifier, or handle , to
every piece of a schematic, including comments and every net
 Grid-Based Schematic Entry:

 Most editors use a grid system for placing components and wires.
 Snapping to the grid simplifies the program's internal workings.
 Grid usage improves compatibility between EDA tools.
 It also promotes cleaner and more readable schematics.

Finding Components:

 Editors allow searching for components by name or using wildcards.

 This is helpful for large schematics where finding specific components can be difficult.

Automatic Naming:

 Some editors can automatically assign reference designators or instance names.

 Prefixes define the starting name for each component type (e.g., R for resistors).
 Numbers in the names are incremented automatically for each new placement.

Unused Reference Designators Report:

 This report helps identify potentially wasted designators in large schematics.

 It might suggest the design could benefit from more hierarchy.

Vectored Cell Instances:

 Used to efficiently place multiple copies of the same cell symbol.

 A special attribute, cell cardinality, specifies the number of copies (e.g., for latches in a data path).
 The bus width and cell cardinality must match to avoid warnings.

Terminal Polarity:

A schematic-entry program can use a terminal attribute to determine which cell

terminals are output terminals and which terminals are input terminals. This attribute is
usually called terminal polarity or terminal direction.

 An attribute helps distinguish input, output, and bidirectional terminals.

 This can help identify nets with only inputs or only outputs.

Fanout and Fanin:

The fanout of a cell measures the driving capability of an output terminal. The fanin of a
cell measures the number of input terminals.

 Fanout measures an output's driving capability (number of standard loads it can drive).
 Fanin measures the number of inputs on a cell.
 Netlist screeners can check if fanout exceeds the total load on a net.

Schematic-Entry tools
1. Icon Edit-in-Place: Some editors offer icon edit-in-place, similar to schematic edit-in-
place for cells, allowing toggling between editing modes.
2. Timestamp Tracking: Schematic-entry programs track cell modifications using
timestamps, alerting designers if subcell timestamps are more recent, indicating
changes.
3. Primitive Cell Editing: Primitive cells in libraries are typically locked. Editing requires
making a copy, but it's usually not accessible or desired by ASIC designers.
4. Version Control: EDA tools maintain backup versions of files, automatically appending
version numbers. Designers can revert to earlier versions if needed.
5. Library Management: Sophisticated tools allow users to create and control access to
libraries during ASIC design, often integrated into larger EDA frameworks.
6. Undo Functionality: Schematic editors offer undo and redo commands, allowing
designers to revert changes within the current editing session.
7. Efficiency Features: Editors provide features like rubber banding for making
connections, automatic wiring, and easy component movement.
8. Connection Validation: Editors may offer visual or audible feedback for accurate wire
connections and prevent ambiguity in four-way connections.
9. Cell Libraries: Managing and selecting components from libraries is essential, and
editors should facilitate easy access to library components.
10. Global Nets and Special Connectors: Large schematics require extending
signals across pages. Global nets and special connectors help in labeling and managing
connections across multiple pages.

Version Control and Backup:

 Editors track cell edits using timestamps. When loading cells, they compare timestamps to subcells to
identify updates.
 Designers are warned about potential inconsistencies if subcells have been modified by others.
 Most EDA tools automatically version files by appending numbers (e.g., Floor.6, Floor.7). This creates
backups in case of mistakes.
 Some advanced tools allow user-controlled libraries with access restrictions.
 You can usually set the number of backup versions kept by the software (version history).
 In case of accidental edits, there's an option to revert to an earlier version.
 More advanced systems use check-out services to prevent conflicts when multiple users edit the
same design.
 It's recommended to rely on software for version control as manual editing can lead to issues.

Undo/Redo Functionality:

 Most schematic editors allow undo/redo commands for a certain number of steps within an editing
session.

Improving Schematic Entry Efficiency:

 Rubber Banding: Drag the cursor to create connections that snap to right angles at the end.
 Automatic Wiring: Define a wire path with clicks, and the editor completes the connections.
 Moving Components with Wires: Move components while automatically dragging connected wires
along.
 Connection Verification:
o Visual or audible feedback confirms successful wire connections.
o Automatic dots at junctions indicate connections.
o Some editors disallow four-way connections to avoid ambiguity about connections between crossing
wires.
 Libraries and Hierarchical Designs:

 A cell library is a collection of reusable symbols. Effective library management is crucial.

 Global Nets: Allow connecting signals (like power/ground) across multiple schematic pages with the
same name.
 Off-Page Connectors: Special symbols represent connections that continue to other schematic
pages.
o More advanced editors can automatically label these connectors with destination page numbers.

Back-Annotation
After entering a schematic, the design undergoes simulation to verify its functionality.
Following this logical design phase, the process moves to ASIC physical design for layout
completion. Only after layout completion can parasitic capacitance and interconnect
delay be determined. This delay information is then back-annotated to the
schematic. Finally, a post-layout simulation ensures that ASIC specifications are met.

1. Simulation: The schematic is simulated to verify it functions as intended (logical design).

2. Physical Design & Layout: The design moves to physical layout, defining the chip's physical
structure.
3. Parasitic Capacitance and Delay: After layout, the interconnect delays caused by parasitic
capacitance are determined.
4. Back-Annotation: This delay information is fed back (annotated) to the original schematic.
5. Post-Layout Simulation: A final simulation is run using the updated delays to ensure the chip meets
specifications

ASIC CONSTRUCTION
The physical design of ASICs is normally divided into system partitioning,
floorplanning, placement, and routing.

 System Partitioning (Town Planning): Similar to how a town planner allocates areas for different
purposes (residential, commercial), this stage divides the entire microelectronic system into functional
blocks (e.g., memory, processor) to be implemented in separate ASICs.
 Floorplanning (Architect): An architect designs the building layout (room arrangement). In ASIC
design, floorplanning defines the overall chip layout, specifying where each functional block from
partitioning will be placed.
 Placement (Builder): The builder physically constructs the building based on the architect's plans.
Similarly, placement assigns specific locations on the chip to each functional block defined in the
floorplan.
 Routing (Electrician): The electrician installs electrical wiring after construction. In ASIC design,
routing connects all the placed blocks with wires, ensuring electrical signals can flow between them.
Physical Design

The Stages of Physical Design (Figure 15.1):

1. System Partitioning: Divides the entire microelectronic system into functional blocks (like memory,
processor) to be implemented in separate ASICs.
2. Floorplanning: Defines the overall chip layout, specifying where each functional block from
partitioning will be placed. This includes allocating space for power, clock wiring, and input/output
pads.
3. Placement: Assigns specific locations on the chip to each functional block defined in the floorplan
and sets aside space for the interconnect to each logic cell. Placement for a gate-array or
standard-cell design assigns each logic cell to a position in a row. Floorplanning and
placement are closely related and are sometimes combined in a single CAD tool.
4. Routing: Routing makes the connections between logic cells. split into two distinct steps,
called global and local routing.

 Global Routing: Global routing determines where the interconnections between the
placed logic cells and blocks will be situated. Only the routes to be used by the
interconnections are decided in this step, not the actual locations of the
interconnections within the wiring areas. is sometimes called loose routing.
 Local Routing: Makes the final connections between logic cells using the information from global
routing. This stage defines the exact width, mask layer, and location of each wire. Local routing
is also known as detailed routing

FIGURE 15.1 Part of an ASIC design flow showing the system partitioning,
floorplanning, placement, and routing steps. These steps may be performed in
a slightly different order, iterated or omitted depending on the type and size of
the system and its ASICs. As the focus shifts from logic to interconnect,
floorplanning assumes an increasingly important role. Each of the steps shown
in the figure must be performed and each depends on the previous step.
However, the trend is toward completing these steps in a parallel fashion and
iterating, rather than in a sequential manner.

Key Points:

 The order of these steps may vary depending on the design size and complexity.
 There may be iterative adjustments between steps.
 The trend is to perform these steps more concurrently rather than strictly sequentially.
 Floorplanning becomes more crucial as the design focuses on interconnections between blocks.

CAD Tools
 To develop a CAD tool for ASIC physical design, each step must be defined with clear
goals and objectives:
 Each physical design step needs clearly defined goals (what must be achieved).
 Objectives (what's desirable to achieve) are additional targets to strive for while reaching the goals.
 These goals and objectives will be used in developing Computer-Aided Design (CAD) tools.

Goals and objectives for each of the ASIC physical design steps are as follows:

System partitioning:

 Goal. Partition a system into a number of ASICs.

 Objectives. Minimize the number of external connections between the ASICs. Keep
each ASIC smaller than a maximum size.

Floorplanning:

 Goal. Calculate the sizes of all the blocks and assign them locations.
 Objective. Keep the highly connected blocks physically close to each other.

Placement:

 Goal. Assign the interconnect areas and the location of all the logic cells within the
flexible blocks.
 Objectives. Minimize the ASIC area and the interconnect density.

Global routing:

 Goal. Determine the location of all the interconnect.

 Objective. Minimize the total interconnect area used.

Detailed routing:

 Goal. Completely route all the interconnect on the chip.

 Objective. Minimize the total interconnect length used.

The reasoning behind the specific steps in ASIC physical design:

 There's no perfect, predetermined way to break down the design process.

 These steps emerged historically as the most practical way to tackle the overall problem.
 The boundaries between steps are flexible. For instance, floorplanning and placement, or placement
and routing, can be combined in some tools.
Methods and Algorithms

The methods and algorithms used in ASIC physical design according to the text:

Methods:

 Heuristic Algorithms: These are used when there's no guaranteed optimal solution. They rely on
rules of thumb to find "good enough" solutions within a reasonable time frame.

Algorithm Complexity:
 The text introduces the concept of Algorithm Complexity using Big O notation (O(f(n))). This notation
describes how the execution time of an algorithm grows with the size of the input (n).
 In ASIC design (where n is typically very large - a large number of transistors or wires), efficient
algorithms are crucial. Here's a breakdown of preferable complexities mentioned:

The function f (n) is usually one of the following kinds:

 f (n) = constant. The algorithm is constant in time. In this case, steps of the
algorithm are repeated once or just a few times. It would be nice if our algorithms
had this property, but it does not usually happen in ASIC design.
 f (n) = log n . The algorithm is logarithmic in time. This usually happens when a
big problem is (possibly recursively) transformed into a smaller one.
 f (n) = n . The algorithm is linear in time. This is a good situation for an ASIC
algorithm that works with n objects.
 f (n) = n log n . This type of algorithm arises when a large problem is split into a
number of smaller problems, each solved independently.
 f (n) = n 2 . The algorithm is quadratic in time and usually only practical for small
ASIC problems.
 If the time it takes to solve a problem increases with the size of the problem at a rate
that is polynomial but faster than quadratic

o O(constant): Ideal scenario, but uncommon in ASIC design.

o O(log n): Occurs when a large problem is divided recursively into smaller ones.
o O(n): Linear growth - desirable for ASIC algorithms.
o O(n log n): Acceptable for some cases.
 Algorithms with complexities of O(n^2) or worse (exponential) are generally not suitable for ASIC
design due to slow execution times for large problems.

NP-Complete Problems:

 The text mentions that most ASIC physical design steps belong to a class of problems known as NP-
complete problems. These are problems where finding the optimal solution is very difficult, and it's
unlikely to find an algorithm that efficiently (polynomial time) guarantees the best answer.

Finding Good Solutions:

 Since finding optimal solutions for NP-complete problems might be impractical, the approach is to find
solutions that are "good enough" and meet the design goals.

Metrics and Objective Functions:

 To measure how close a solution is to being good, designers define metrics that quantify how well the
solution achieves the goals and objectives set for each design step (area, power consumption, etc.).
 These metrics are often combined into a single measurement function or objective function.
 If the goal is to minimize a metric (like area), the objective function becomes a cost function.
 Conversely, if maximizing a metric (like speed), the function becomes a gain function.
 Finding Solutions with Algorithms:

 CAD tools rely on algorithms to solve physical design problems within a reasonable time.
 Often, there's no perfect solution, so these tools use heuristic (rule-of-thumb) algorithms to find good
enough solutions.
 The effectiveness of an algorithm is measured by its time complexity (how long it takes to run based
on problem size).
 In ASIC design, where problems are typically large (n), we aim for algorithms with complexity lower
than n^2 (quadratic).
 The worst-case scenario is exponential complexity, which is impractical for ASIC design.

NP-Complete Problems and Measurement:

 Many ASIC physical design problems are NP-complete, meaning it's unlikely to find an exact optimal
solution in polynomial time.
 Since we can't find the absolute best solution, we need ways to measure how close a solution is to
optimal.
 This measurement is done using a function that combines various factors related to the design goals
and objectives.
 This function can be a cost function (minimized) or a gain function (maximized).

Challenges and Trade-offs:

 ASIC designers consider factors like speed, area, and power consumption during design.
 Current CAD tools are limited and can't handle these trade-offs on their own.
 They can only find solutions based on a few basic objectives provided by the designer.

System partitioning:

System Partitioning:

 When a functional block is too large for a single ASIC, it's divided (partitioned) based on specified
goals and objectives.
 Common goals include minimizing the number of pins per ASIC (reducing packaging cost).
 CAD tools can assist with system partitioning.

SPARCstation 1 System Breakdown (Figure 15.2):

 The system consists of:

o 9 custom ASICs (for specific functions)
o Memory subsystems (CPU cache, RAM, memory cache)
o Standard off-the-shelf chips (ASSPs) for I/O, time-of-day, and video memory
o An EPROM (programmable memory)
o An analog-to-digital converter (DAC)

Factors Affecting Partitioning Decisions:

 The choice between using custom ASICs or pre-designed ASSPs influences partitioning.
 Other factors influencing decisions (not aided by CAD tools):
o Time-to-market pressure
o Past experience with a technology
o Design reusability from previous products
o Difficulty in quantifying these factors makes them unsuitable for CAD tool support.

Limitations of CAD Tools:

 While CAD tools can't answer questions like "what's the cheapest way to build the system?", they can
help with:
o "How to split the circuit into pieces that fit on a chip?"
Estimating ASIC Size
The actual size of a memory will depend on (1) the required access time, (2) the use of
synchronous or asynchronous read or write, (3) the number and type of ports (read–
write), (4) the use of special design rules, (5) the number of interconnect layers
available, (6) the RAM architecture (number of devices in RAM cell), and (7) the process
technology (active pull-up devices or pull-up resistors).

Figure 15.3 (a) shows the typical size of SRAM constructed on an ASIC. These figures are
based on the use of a RAM compiler (as opposed to building memory from flip-flops or
latches) using a standard CMOS ASIC process, typically using a six-transistor cell.

FIGURE 15.3 (a) ASIC memory size. These figures are for static RAM constructed using
compilers in a 2LM ASIC process, but with no special memory design rules. The actual
area of a RAM will depend on the speed and number of read–write ports. (b) Multiplier
size for a 2LM process. The actual area will depend on the multiplier architecture and
speed.

FPGA Partitioning
 Designing ASICs involves many considerations during partitioning, making it complex.
 There are currently no commercial tools that effectively address all these complexities.
 For such cases, a simple spreadsheet might be the most practical tool.
 Partitioning a group of logic cells into Field-Programmable Gate Arrays (FPGAs).
 This is considered "easier" if all the FPGAs are identical.

Partitioning Methods
System partitioning requires goals and objectives, methods and algorithms to find
solutions, and ways to evaluate these solutions.

The goal of partitioning is to divide this part of the system so that each partition
is a single ASIC. To do this we may need to take into account any or all of the
following objectives:

 A maximum size for each ASIC

 A maximum number of ASICs
 A maximum number of connections for each ASIC
 A maximum number of total connections between all ASICs

Measuring Connectivity

FIGURE 15.6 Networks, graphs, and partitioning. (a) A network containing circuit logic
cells and nets. (b) The equivalent graph with vertexes and edges. For example: logic cell
D maps to node D in the graph; net 1 maps to the edge (A, B) in the graph. Net 3 (with
three connections) maps to three edges in the graph: (B, C), (B, F), and (C, F).
(c) Partitioning a network and its graph. A network with a net cut that cuts two nets.
(d) The network graph showing the corresponding edge cut. The net cutset in c contains
two nets, but the corresponding edge cutset in d contains four edges. This means a
graph is not an exact model of a network for partitioning purposes.
 Networks and Graphs:
o An ASIC circuit can be represented as a network of logic cells connected by electrical nets.
o This network can be modeled by a mathematical graph with vertices (representing logic cells) and
edges (representing connections between cells).
 Partitioning for ASIC Design:
o ASICs are often built by dividing the circuit into smaller blocks.
o Graph theory helps analyze how to partition the network into these blocks while minimizing the
number of connections between them.
o Minimizing connections reduces the size and complexity of the final ASIC.
 Limitations of Graph Model:
o A net can connect more than two logic cells, while a graph edge only connects two vertices.
o When partitioning the network, cutting a net with multiple connections creates multiple edge cuts in
the graph model.
o This means the number of connections between partitions might be underestimated by the graph
model.

the network shown in Figure 15.6 (c) into two parts, corresponding to creating two ASICs,
we can divide the network’s graph in the same way. Figure 15.6 (d) shows a possible
division, called a cutset. We say that there is a net cutset (for the network) and an edge
cutset (for the graph). The connections between the two ASICs are external connections,
the connections inside each ASIC are internal connections.

Notice that the number of external connections is not modeled correctly by the network
graph. When we divide the network into two by drawing a line across connections, we
make net cuts. The resulting set of net cuts is the net cutset. The number of net cuts we
make corresponds to the number of external connections between the two partitions.
When we divide the network graph into the same partitions we make edge cuts and we
create the edge cutset. We have already shown that nets and graph edges are not
equivalent when a net has more than two terminals.

A Simple Partitioning Example

(a) shows a simple network we need to partition [ Goto and Matsud, 1986]. There are 12
logic cells, labeled A–L, connected by 12 nets (labeled 1–12). At this level, each logic cell
is a large circuit block and might be RAM, ROM, an ALU, and so on. Each net might also
be a bus, but, for the moment, we assume that each net is a single connection and all
nets are weighted equally. The goal is to partition our simple network into ASICs. Our
objectives are the following:

 Use no more than three ASICs.

 Each ASIC is to contain no more than four logic cells.
 Use the minimum number of external connections for each ASIC.
 Use the minimum total number of external connections.

Figure 15.7 (b) shows a partitioning with five external connections; two of the ASICs have
three pins; the third has four pins.We might be able to find this arrangement by hand,
but for larger systems we need help.
 (a) (b) (c)

FIGURE 15.7 Partitioning example. (a) We wish to partition this network into three ASICs
with no more than four logic cells per ASIC. (b) A partitioning with five external
connections (nets 2, 4, 5, 6, and 8)—the minimum number. (c) A constructed partition
using logic cell C as a seed. It is difficult to get from this local minimum, with seven
external connections (2, 3, 5, 7, 9,11,12), to the optimum solution of b.

Splitting a network into several pieces is a network partitioning problem. In the following
sections we shall examine two types of algorithms to solve this problem and describe
how they are used in system partitioning.

1. constructive partitioning- which uses a set of rules to find a solution.

2. iterative partitioning improvement (or iterative partitioning refinement), which
takes an existing solution and tries to improve it.

Constructive Partitioning

 Goals of partitioning:
o Minimize the number of connections between ASICs (external connections).
o Limit the size and complexity of each ASIC (number of logic cells per ASIC).

The most common constructive partitioning algorithms use seed growth or cluster
growth. A simple seed-growth algorithm for constructive partitioning consists of the
following steps:

1. Start a new partition with a seed logic cell.

2. Consider all the logic cells that are not yet in a partition. Select each of these logic
cells in turn.
3. Calculate a gain function, g(m) , that measures the benefit of adding logic cell m to
the current partition. One measure of gain is the number of connections between
logic cell m and the current partition.
4. Add the logic cell with the highest gain g(m) to the current partition.
5. Repeat the process from step 2. If you reach the limit of logic cells in a partition,
start again at step 1.

The algorithm starts with the choice of a seed logic cell ( seed module, or just seed). The
logic cell with the most nets is a good choice as the seed logic cell. You can also use a
set of seed logic cells known as a cluster. Some people also use the term clique —
borrowed from graph theory. A clique of a graph is a subset of nodes where each pair of
 nodes is connected by an edge—like your group of friends at school where everyone
knows everyone else in your clique.

Constructive partitioning is a technique used in ASIC design to divide a circuit into smaller blocks
(ASICs) by building partitions from scratch. Here's how it works:

1. Seed Selection:
o The algorithm starts by choosing a seed element, which can be:
 A single logic cell: The logic cell with the most connections (nets) is a good initial choice.
 A cluster of logic cells: This can be a group of interconnected cells or even an entire schematic page
representing a functional block in your design.
 A clique (graph theory term): This refers to a group of cells where every cell is connected to every
other cell within the group. Similar to a close-knit group of friends where everyone knows everyone
else.
2. Cell Addition:
o Once you have a seed, the algorithm considers all the remaining logic cells in the circuit (not yet
assigned to a partition).
o For each un-assigned cell, a gain function is calculated. This function estimates the benefit of adding
that cell to the current partition.
o The gain function typically considers the number of connections between the cell and the existing
elements in the partition. More connections generally indicate a better fit for the cell within that
partition.
3. Growth and Repeat:
o The cell with the highest gain (most connections to the current partition) is then added to that
partition.
o Steps 2 and 3 (considering un-assigned cells and adding the best fit) are repeated until the partition
reaches its size limit (e.g., maximum number of cells allowed per ASIC).
4. Multiple Partitions:
o Once a partition is full, a new partition is created, and the process restarts with a new seed selection
(another logic cell, cluster, or clique).
o This continues until all the logic cells in the circuit are assigned to a partition, effectively dividing the
entire circuit into separate ASIC blocks.

Choosing the Right Seed:

The seed selection plays a crucial role in constructive partitioning. A good seed can lead to a more
efficient partitioning with fewer external connections between ASICs. Here are some tips:

 Cells with Many Connections: These cells likely have connections spread across different parts of
the circuit. Including them early can help guide the formation of well-connected partitions.
 Functional Blocks: If your design uses pre-defined functional blocks (schematic pages or Verilog
modules), using them as seeds can ensure these blocks stay together within an ASIC.
 Experimentation: Sometimes trying different seed choices can lead to better partitioning results.

Limitations:

 Constructive partitioning is a greedy approach. It makes local decisions (adding the best fitting cell at
each step) which may not always lead to the globally optimal solution (absolute minimum number of
external connections).
 The gain function used can significantly impact the final outcome. Choosing the right function
depends on your specific partitioning goals (minimizing connections, balancing cell count across
ASICs, etc.).
 Iterative Partitioning Improvement
The most common iterative improvement algorithms are based on interchange
and group migration. The process of interchanging (swapping) logic cells in an
effort to improve the partition is an interchange method. If the swap improves
the partition, we accept the trial interchange; otherwise we select a new set of
logic cells to swap.

(b) (c)

Figure 15.7 (c) shows a partitioning of the network of part a using a constructed
partitioning algorithm with logic cell C as the seed. To get from the solution shown in
part c to the solution of part b, which has a minimum number of external connections,
requires a complicated swap. The three pairs: D and F, J and K, C and L need to be
swapped—all at the same time. It would take a very long time to consider all possible
swaps of this complexity.

A simple interchange algorithm considers only one change and rejects it immediately if it
is not an improvement. Algorithms of this type are greedy algorithms in the sense that
they will accept a move only if it provides immediate benefit.

a greedy algorithm is not prepared to walk over a hill to see if there is a better solution in
the next valley. This type of problem occurs repeatedly in CAD algorithms.

 Limitations of Swapping-based Partitioning:

o The example shows a partition with a local minimum (solution in Fig 15.7c).
o Reaching the optimal solution (Fig 15.7b) requires complex swaps of multiple elements at once,
which is computationally expensive for simple algorithms.

Greedy Algorithms and Local Minimum:

 Simple partitioning algorithms often use a greedy approach, where they only consider single swaps
and accept them if they immediately improve the solution.
 This approach can lead the algorithm to a local minimum, a solution that seems good locally but isn't
necessarily the best overall
Group migration consists of swapping groups of logic cells between partitions. The group
migration algorithms are better than simple interchange methods at improving a solution
but are more complex. Almost all group migration methods are based on the powerful
and general Kernighan–Lin algorithm ( K–L algorithm) that partitions a graph, The
problem of dividing a graph into two pieces, minimizing the nets that are cut, is
the min-cut problem—a very important one in VLSI design.

The Kernighan–Lin Algorithm

Figure 15.8 illustrates some of the terms and definitions needed to describe the K–L
algorithm. External edges cross between partitions; internal edges are contained inside a
partition. Consider a network with 2 m nodes (where m is an integer) each of equal size.
If we assign a cost to each edge of the network graph, we can define a cost matrix C
= c ij , where c ij = c ji and c ii = 0. If all connections are equal in importance, the
elements of the cost matrix are 1 or 0, and in this special case we usually call the matrix
the connectivity matrix. Costs higher than 1 could represent the number of wires in a
bus, multiple connections to a single logic cell, or nets that we need to keep close for
timing reasons.

FIGURE 15.8 Terms used by the Kernighan–Lin partitioning algorithm. (a) An example
network graph. (b) The connectivity matrix, C;

Suppose we already have split a network into two partitions, A and B , each
with m nodes (perhaps using a constructed partitioning). Our goal now is to swap
nodes between A and B with the objective of minimizing the number of
external edges connecting the two partitions. Each external edge may be
weighted by a cost, and our objective corresponds to minimizing a cost function
that we shall call the total external cost, cut cost, or cut weight, W :

In Figure 15.8 (a) the cut weight is 4 (all the edges have weights of 1).

In order to simplify the measurement of the change in cut weight when we interchange
nodes, we need some more definitions. First, for any node a in partition A , we define
an external edge cost, which measures the connections from node a to B ,
For example, in Figure 15.8 (a) E 1 = 1, and E 3 = 0. Second, we define the internal edge
cost to measure the internal connections to a ,

So, in Figure 15.8 (a), I 1 = 0, and I 3 = 2. We define the edge costs for partition B in a
similar way (so E 8 = 2, and I 8 = 1). The cost difference is the difference between
external edge costs and internal edge costs,

Thus, in Figure 15.8 (a) D 1 = 1, D 3 = – 2, and D 8 = 1. Now pick any node in A , and any
node in B . If we swap these nodes, a and b, we need to measure the reduction in cut
weight, which we call the gain, g . We can express g in terms of the edge costs as
follows:

The last term accounts for the fact that a and b may be connected. So, in Figure 15.8 (a),
if we swap nodes 1 and 6, then g = D 1 + D 6 – 2 c 16 = 1 + 1. If we swap nodes 2 and 8,
then g = D 2 + D 8 – 2 c 28 = 1 + 2 – 2.

The K–L algorithm finds a group of node pairs to swap that increases the gain even
though swapping individual node pairs from that group might decrease the gain. First we
pretend to swap all of the nodes a pair at a time. Pretend swaps are like studying chess
games when you make a series of trial moves in your head.

This is the algorithm:

1. Find two nodes, a i from A , and b i from B , so that the gain from swapping them is
a maximum. The gain is

2. Next pretend swap a i and b i even if the gain g i is zero or negative, and do not
consider a i and b i eligible for being swapped again.
 3. Repeat steps 1 and 2 a total of m times until all the nodes of A and B have been
pretend swapped. We are back where we started, but we have ordered pairs of
nodes in A and B according to the gain from interchanging those pairs.
4. Now we can choose which nodes we shall actually swap. Suppose we only swap
the first n pairs of nodes that we found in the preceding process. In other words we
swap nodes X = a 1 , a 2 ,…, a n from A with nodes Y = b 1 , b 2 ,…, b n from B. The
total gain would be

5. We now choose n corresponding to the maximum value of G n .

If the maximum value of G n > 0, then we swap the sets of nodes X and Y and thus
reduce the cut weight by G n . We use this new partitioning to start the process again at
the first step. If the maximum value of G n = 0, then we cannot improve the current
partitioning and we stop. We have found a locally optimum solution.

FIGURE 15.9 Partitioning a graph using the Kernighan–Lin algorithm. (a) Shows how
swapping node 1 of partition A with node 6 of partition B results in a gain of g = 1. (b) A
graph of the gain resulting from swapping pairs of nodes. (c) The total gain is equal to
the sum of the gains obtained at each step
The K–L algorithm works well for partitioning graphs. However, there are the following
problems that we need to address before we can apply the algorithm to network
partitioning:

 It minimizes the number of edges cut, not the number of nets cut.
 It does not allow logic cells to be different sizes.
 It is expensive in computation time.
 It does not allow partitions to be unequal or find the optimum partition size.
 It does not allow for selected logic cells to be fixed in place.
 The results are random.
 It does not directly allow for more than two partitions.

To implement a net-cut partitioning rather than an edge-cut partitioning, we can just

keep track of the nets rather than the edges.

To represent nets with multiple terminals in a network accurately, we can extend the
definition of a network graph. Figure 15.10 shows how a hypergraph with a special type
of vertex, a star, and a hyperedge, represents a net with more than two terminals in a
network.

In the K–L algorithm, the internal and external edge costs have to be calculated for all
the nodes before we can select the nodes to be swapped. Then we have to find the pair
of nodes that give the largest gain when swapped. This requires an amount of computer
time that grows as n 2 log n for a graph with 2n nodes. This n 2 dependency is a major
problem for partitioning large networks.

The Fiduccia–Mattheyses algorithm (the F–M algorithm) is an extension to the K–L

algorithm that addresses the differences between nets and edges and also reduces
the computational effort. The key features of this algorithm are the following:

 Only one logic cell, the base logic cell, moves at a time. In order to stop the
algorithm from moving all the logic cells to one large partition, the base logic cell
is chosen to maintain balance between partitions. The balance is the ratio
of total logic cell size in one partition to the total logic cell size in the
other. Altering the balance allows us to vary the sizes of the partitions.
 Critical nets are used to simplify the gain calculations. A net is a critical
net if it has an attached logic cell that, when swapped, changes the
number of nets cut. It is only necessary to recalculate the gains of logic cells on
critical nets that are attached to the base logic cell.
  The logic cells that are free to move are stored in a doubly linked list. The
lists are sorted according to gain. This allows the logic cells with maximum
gain to be found quickly.

These techniques reduce the computation time so that it increases only slightly
more than linearly with the number of logic cells in the network, a very important
improvement.

Kernighan and Lin suggested simulating logic cells of different sizes by

clumping s logic cells together with highly weighted nets to simulate a logic cell
of size s . The F–M algorithm takes logic-cell size into account as it selects a logic
cell to swap based on maintaining the balance between the total logic-cell size
of each of the partitions. To generate unequal partitions using the K–L algorithm, we
can introduce dummy logic cells with no connections into one of the partitions.
The F–M algorithm adjusts the partition size according to the balance
parameter.

Methods based on the K–L algorithm find locally optimum solutions in a random fashion.
There are two reasons for this. The first reason is the random starting partition. The
second reason is that the choice of nodes to swap is based on the gain. The choice
between moves that have equal gain is arbitrary

The Look-ahead Algorithm

Both the K–L and F–M algorithms consider only the immediate gain to be made by
moving a node. When there is a tie between nodes with equal gain (as often happens),
there is no mechanism to make the best choice. Figure 15.11 shows an example of two
nodes that have equal gains, but moving one of the nodes will allow a move that has a
higher gain later.

We call the gain for the initial move the first-level gain. Gains from subsequent moves
are then second-level and higher gains. We can define a gain vector that contains these
gains. Figure 15.11 shows how the first-level and second-level gains are calculated.
Using the gain vector allows us to use a look-ahead algorithm in the choice of nodes to
be swapped. This reduces both the mean and variation in the number of cuts in
the resulting partitions.
FIGURE 15.11 An example of network partitioning that shows the need to look ahead
when selecting logic cells to be moved between partitions. Partitionings (a), (b), and (c)
show one sequence of moves, partitionings (d), (e), and (f) show a second sequence. The
partitioning in (a) can be improved by moving node 2 from A to B with a gain of 1. The
result of this move is shown in (b). This partitioning can be improved by moving node 3
to B, again with a gain of 1. The partitioning shown in (d) is the same as (a). We can
move node 5 to B with a gain of 1 as shown in (e), but now we can move node 4 to B
with a gain of 2.