Department of Computer Science and Engineering
CSE 345 Post-Lab Report
Course Name: Digital Logic Design
Course Code: CSE 345
Section No: 01
Experiment No: 01
Name of the Experiment: Schematic and Structural Verilog Simulation of
Combinational Logic Circuits.
Date of allocation: 29 June 2025
Date of submission: 19 July 2025
Submitted To:
Dr. Md Sawkat Ali
Associate Professor
Department of Computer Science & Engineering
Submitted By:
Group Members:
Student’s Name: Md. Khalid Hasan
Student’s ID: 2023-3-50-050
Student’s Name: Tasnimul Hasan
Student’s ID: 2023-3-50-053
1. Experiment Objectives:
To learn schematic simulation of combinational logic circuits using Quartus
II software.
To learn structural Verilog simulation of combinational logic circuits using
Quartus II software.
2. Circuit Diagrams:
Practically, we have done this circuit which is given below.2nd part
Fig-01: Schematic Diagram of a Two-Input Combinational Circuit
The Boolean expression for the output S of the combinational circuit shown in
Figure 1 is derived as follows: The circuit consists of two NOT gates, two AND
gates, and one OR gate.
Therefore, the Boolean expression for the output S is: S= A'B + A B'
Here is the Truth table:
A B S
0 0 0
0 1 1
1 0 1
1 1 0
3. Equipment and Components Needed:
AND2 logic gate (symbols).
OR2 logic gate (symbols).
NOT logic gate (symbols)
Input pins (input symbols)
Output pin (output symbols)
Wires for connections
Orthogonal Node Tool icon (for connecting wires in Quartus II)
4. Simulation: When A and B are different, S is high (1); when they are the
same, S is low (0).
Fig-02: Simulation output.
Simulation of Verilog Code:
This Verilog code directly describes the interconnection of gates, mirroring the
schematic diagram. ~A and ~B represent the inverted inputs, and w1 and w2 are
intermediate wires connecting the AND gate outputs to the OR gate input. show
now
Fig-03: Editor window.
Solution to Post-Lab Report Questions and Lab Procedure/ Workflow:
Question-01:
1. Sol: The Boolean expression and the truth table of the output S of the
combinational circuit of Figure 7.
Boolean expression: S= A'B'C + A'BC' + AB'C' + ABC
here is the Truth table:
A B C S
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Question-02: the structural Verilog code for describing the combinational circuit
of Figure 7
Fig-04: Verilog Code for the Three-Input Combinational Circuit
Circuit Diagrams:
Fig: Schematic Diagram of a three -Input Combinational Circuit
Simulation:
Fig: Simulation output the combinational circuit of Figure 7.
Experimental Datasheet:
Figure 7 shows the physical implementation of a combinational logic circuit on a
breadboard using various integrated circuits (ICs) and connecting wires.
Discussion:
This experiment successfully demonstrated the design and simulation of
combinational logic circuits using Quartus II. We implemented both a two-input
logic function and a three-input circuit using schematic capture and structural
Verilog. All simulations consistently matched the expected truth tables, validating
our designs. The lab reinforced the translation of Boolean expressions into
hardware and provided practical experience with digital design tools. Minor
challenges involved ensuring correct connections and Verilog syntax. Overall, the
experiment provided a comprehensive understanding of combinational logic circuit
analysis, design, and simulation.
Conclusion:
This experiment successfully achieved its objectives of simulating combinational
logic circuits using Quartus II. We designed and verified both two-input and three-
input circuits, confirming theoretical behavior through simulation. The lab
provided valuable experience with EDA tools, strengthening our understanding of
logic gates, Boolean algebra, and the process of digital circuit design and
verification.
