Unit 5: Computer Arithmetic
.1 Explain how addition and subtraction operation is performed with
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signed-magnitude data using block diagram.
hen adding and subtracting signed-magnitude numbers, you need to consider both the
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signs and the magnitudes of the numbers.
● A
ddition:If the signs of the two numbers are thesame, you add their magnitudes and
keep the same sign1. If the signs are different, yousubtract the smaller magnitude from
the larger one2. The sign of the result is the sameas the number with the larger
magnitude3. If the magnitudes are equal, the resultis zero4.
● S
ubtraction:To perform subtraction, you first changethe sign of the subtrahend and
then follow the rules of addition5.
The hardware uses an
dder/subtractorunit, amagnitude comparatorto determinethe larger number, and asign
a
logicunit to handle the signs6.
.2 Explain how addition and subtraction operation is performed with signed-2's
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complement data using block diagram.
igned-2's complement representation simplifies arithmetic because both addition and
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subtraction can be performed using only addition.
● Addition:The two numbers are added along with theirsign bits7. Any carry-out from the
sign bit position is ignored8. The result is in 2'scomplement form.
● S
ubtraction:To subtract a number, you take its2'scomplementand add it to the other
number9. Taking the 2's complement involves inverting all the bits and adding 110.
The block diagram for this operation is relatively simple, as it mainly consists of an
adderand control logic for complementing the subtrahendduring a subtraction operation11.
.3 Explain how multiplication operation is performed using successive shift and
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add operations. Support your answer with block diagram for hardware for
multiply operation.
inary multiplication can be performed by a series of shift and add operations, similar to long
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multiplication. The process is as follows:
1. Initialize aproduct register (A)to zero and asequencecounterwith the number of bits
in the multiplier.
2. Check the least significant bit (LSB) of themultiplierregister (Q).
3. If the LSB is 1, add themultiplicand register (B)to the product register (A).
4. If the LSB is 0, do nothing.
5. Right-shift the combined register AQ by one position.
6. Decrement the sequence counter.
7. Repeat the process until the sequence counter is zero.
The hardware includes registers for the
ultiplicand (B),multiplier (Q), andproduct (A),along with anadderand asequence
m
counter12.
.4 Explain Booth algorithm for multiplying binary integers in signed-2's
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complement representation. Support your answer with block diagram for
hardware implementation for Booth Algorithm.
ooth's algorithm is an efficient method for multiplying signed-2's complement binary
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numbers. It treats consecutive 1s and 0s in the multiplier differently to reduce the number of
additions required.
The algorithm works by examining pairs of bits in the multiplier, starting from the least
significant bit (LSB), and a bit to its right (Qn+1).
● If the pair is01, you add the multiplicand to theaccumulator.
● If the pair is10, you subtract the multiplicand (i.e.,add its 2's complement).
● If the pair is 00 or 11, you don't perform any addition or subtraction.
After each step, you perform an arithmetic right shift on the accumulator and multiplier
registers. This process is repeated for all bits of the multiplier.
he hardware uses registers for the multiplicand, a partial product accumulator, the multiplier,
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and a single bit to the right of the multiplier for bit-pair checking13.
.5 What is the advantage of array multiplier as compared to other multipliers?
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Draw logic circuit diagram for 2 bit by 2 bit array multiplier and explain its
working.
The main advantage of an
rray multiplieris itshigh speed14. It performsmultiplication in a single step using a
a
combinational logic circuit, unlike sequential multipliers that use a sequence of shifts and
adds. This parallel nature makes it much faster15.
A
-bit by 2-bit array multiplieruses fourAND gatesand twohalf-adders16. Each AND gate
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multiplies one bit from the multiplicand with one bit from the multiplier. The outputs of these
AND gates (partial products) are then summed up using half-adders to produce the final
product17.
.6 With the help of a block diagram show register organization for floating-point
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arithmetic operations and explain the same.
loating-point numbers are represented by a mantissa and an exponent. The register
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organization for floating-point operations requires dedicated registers to handle these
components separately18.
The block diagram includes:
● xponent Registers:To hold the exponents of the twonumbers.
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● Mantissa Registers:To hold the mantissas of the twonumbers.
● Sign Bits:To hold the signs of the numbers.
● Specialized Hardware: Includes an exponent adder/subtractor and a mantissa
multiplier/divider.
The system also needs a separate
alignment stageto make the exponents equal beforeaddition or subtraction19.
.7 Discuss algorithm steps for addition and subtraction of floating-point
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numbers.
Floating-point addition and subtraction involve four main steps20:
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1 heck for Zero:Check if either operand is zero. Ifso, the result is the other operand.
2. Align the Mantissas:Shift the mantissa of the numberwith the smaller exponent to the
right and increment its exponent until both exponents are equal.
3. Add or Subtract the Mantissas:Perform the additionor subtraction on the aligned
mantissas.
4. Normalize the Result:Adjust the mantissa and exponentso that the mantissa is within
the standard range (e.g., 1≤mantissa<10). The exponent is adjusted accordingly. If there's
an overflow or underflow, handle it.
Q.8 Discuss algorithm steps for multiplication of floating-point numbers.
loating-point multiplication is simpler than addition because you don't need to align the
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mantissas21. The steps are:
1. A dd the Exponents:The exponents of the two numbersare added. The base is then
subtracted from the sum to correct for the biased representation.
2. Multiply the Mantissas:The mantissas are multiplied.
3. Determine the Sign:The sign of the result is theXOR of the signs of the two numbers.
4. Normalize the Result:The mantissa and exponent areadjusted to fit the standard
format.
Q.9 Discuss algorithm steps for division of floating-point numbers.
Floating-point division also avoids the mantissa alignment step22. The steps are:
1. S ubtract the Exponents:The exponent of the divisoris subtracted from the exponent of
the dividend.
2. Divide the Mantissas:The mantissa of the dividendis divided by the mantissa of the
divisor.
3. Determine the Sign:The sign of the result is theXOR of the signs of the two numbers.
4. Normalize the Result:The mantissa and exponent areadjusted to the correct format.
Q.10 What is Decimal Arithmetic Unit?
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ecimal Arithmetic Unit (DAU)is a part of a computer'scentral processing unit (CPU) that
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is designed to perform arithmetic operations directly ondecimal numbers23. Instead of
converting decimal numbers to binary for calculations, a DAU works with decimal
representations like
CD (Binary-Coded Decimal)24. This is particularlyuseful in business and financial
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applications where exact decimal representation is required and rounding errors from binary
conversion are unacceptable25.
.11 How will you implement arithmetic operations of addition, subtraction,
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multiplication and division using decimal data?
Decimal arithmetic operations are implemented using BCD.
● Addition and Subtraction:BCD numbers are added orsubtracted bit by bit26. The result
f each 4-bit group is checked to see if it exceeds 9 or if there is a carry27. If it does, a
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correction (adding or subtracting 6) is applied to ensure the result is in valid BCD format.
● Multiplication and Division:These operations aremore complex28. They can be
performed using repeated decimal addition and subtraction, respectively29.
Unit 6: Pipeline & Vector Processing
Q.1 State advantage and disadvantage of parallel processing.
● A
dvantages:
○ Increased Speed:Parallel processing significantlyspeeds up computation by
executing multiple instructions or processes simultaneously30.
○ P
roblem Solving:It allows for solving larger andmore complex problems that would
be too slow for a single processor31.
○ C ost Savings:It can be more cost-effective to usemultiple smaller processors than
a single, very fast one.
Disadvantages:
●
○ Increased Complexity:Writing parallel programs ismore complex and difficult than
writing sequential programs32.
○ S
ynchronization Overhead:The processors need to communicateand synchronize,
which adds overhead and can limit performance gains33.
○ Hardware Cost:The initial cost of parallel processinghardware can be high.
Q.2 Discuss classification of Parallel Processing by M. J. Flynn.
lynn's classificationcategorizes computer architecturesbased on how they handle
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instruction streams and data streams34. There arefour main types:
1. S
ISD (Single Instruction, Single Data):A conventional uniprocessor with a single
instruction stream operating on a single data stream35.
2. S
IMD (Single Instruction, Multiple Data):Multipleprocessors execute the same
instruction on different data simultaneously36. Thisis common in array processors.
3. M
ISD (Multiple Instruction, Single Data):Multipleprocessors execute different
instructions on the same data stream37. This architectureis not widely used.
4. M
IMD (Multiple Instruction, Multiple Data):Multipleprocessors execute different
instructions on different data streams simultaneously38.This is the most common form of
parallel processing, used in multicore processors and multiprocessor systems.
Q.3 What is pipeline processing? Explain with the help of an example.
ipeline processingis a technique that breaks downa complex task into a series of smaller,
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sequential subtasks, called segments, which are executed in a continuous, overlapping
fashion39. This allows multiple instructions to bein different stages of execution at the same
time, increasing the throughput of the processor40.
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xample:Consider a task with four stages: Fetch,Decode, Execute, and Write-back.
Without a pipeline, each instruction completes all four stages before the next one begins.
In a pipeline, while instruction 1 is in the Execute stage, instruction 2 can be in the
Decode stage, and instruction 3 can be in the Fetch stage. This creates an assembly-line
effect, completing one instruction per clock cycle once the pipeline is full41.
Q.4 Draw and explain block diagram for a 4-segment pipeline.
4-segment pipeline divides an instruction's execution into four stages. Each stage is
A
separated by a register to hold the output of the previous stage, acting as a buffer.
The segments are:
● S1:Instruction Fetch (FI)42
● S2:Instruction Decode and Operand Fetch (DA)43
● S3:Execution (EX)44
● S4:Write-back (WB)45
he output of segment
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Siis stored in a register that becomes the input for segment Si+1, allowing for a
continuous flow of instructions46.
Q.5 Differentiate between arithmetic pipeline and instruction pipeline.
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rithmetic Pipeline:This pipeline breaks down a complexarithmetic operation (like
floating-point addition or multiplication) into multiple stages. For example, floating-point
addition can be segmented into exponent comparison, mantissa alignment, addition, and
normalization47.
● I nstruction Pipeline:This pipeline divides the executionof an entire instruction into
stages, such as fetching, decoding, executing, and writing back the result. It's used to
increase the overall instruction throughput of the CPU48.
.6 Draw and explain block diagram for pipeline for floating-point addition and
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subtraction.
A floating-point adder can be segmented into four pipeline stages to increase throughput49.
The four stages are:
1. Compare Exponents:Subtract the exponents to findtheir difference50.
2. A
lign Mantissas:Shift the mantissa of the numberwith the smaller exponent to match
the larger exponent51.
3. Add/Subtract Mantissas:Perform the addition or subtractionon the mantissas52.
4. N
ormalize Result:Adjust the mantissa and exponentto fit the standard floating-point
format53.
Q.7 Draw and explain flowchart for 4-segment CPU pipeline (instruction pipeline).
A 4-segment CPU pipeline breaks down instruction execution to improve throughput54.
The flowchart illustrates the four stages:
1. Fetch Instruction (FI):Read the instruction frommemory55.
2. D
ecode Instruction (DA):Decode the instruction andfetch the operands from
registers56.
3. Execute Instruction (EX):Perform the operation specifiedby the instruction57.
4. Write Back (WB):Write the result to a register ormemory58.
he flowchart shows how each stage operates in parallel with the others, processing
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different instructions at the same time59.
Q.8 Explain Vector Processing.
ector processingis a form of parallel processingthat involves operations on entire arrays or
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"vectors" of data with a single instruction60. Insteadof processing one element at a time, a
v ector processor applies the same operation to many data elements simultaneously61. This is
highly efficient for tasks with repetitive calculations on large data sets, as it reduces the
overhead of instruction fetching and decoding62.
Q.9 Give examples of application areas which utilize vector processing.
Vector processing is used in applications that involve large, repetitive computations, such as:
● S
cientific and engineering calculations:Fluid dynamics,weather forecasting, and
molecular modeling63.
● Image and signal processing:Filtering, compression,and analysis of large data sets64.
● M
achine learning and artificial intelligence:Trainingneural networks and other
data-intensive algorithms.
Q.10 What is memory interleaving?
emory interleavingis a technique used to improvememory access speed by dividing the
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main memory into multiple independent modules65. Eachmodule can be accessed
independently, so a CPU or a vector processor can access multiple memory locations
simultaneously. This is achieved by distributing the addresses sequentially across the
modules66. For example, address 0 would be in module0, address 1 in module 1, and so on.
This allows for faster data retrieval for sequential data streams, which is particularly beneficial
for pipelined and vector processors67.
Q.11 What is an array processor?
An
rray processoris a processor that performs computationson large arrays of data68. There
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are two main types:
● A
ttached Array Processor:A separate unit connectedto a general-purpose host
computer69. The host computer handles the main programflow, while the array processor
handles the intensive array computations.
● S
IMD Array Processor:A system with multiple processingelements that execute the
same instruction on different data simultaneously70.
Q.12 Differentiate between attached array processor and SIMD array processor.
Feature Attached Array Processor SIMD Array Processor
Architecture co-processor for a host
A stand-alone computer
A
computer. system.
Control he host computer controls
T central control unit
A
the overall program flow. broadcasts the same
instruction to all processing
elements.
Data Flow he host sends data to the
T ach processing element
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array processor for has its own data memory.
computation.
Application sed for speeding up
U sed for tasks that can be
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specific, compute-intensive broken down into identical
tasks. operations on different
data, like image processing.
.13 Draw and explain block diagram for attached array processor with host
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computer.
An
ttached array processoris designed to enhance theperformance of a host computer by
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handling intensive numerical calculations71.
The system consists of:
● Host Computer:A general-purpose computer that managesthe overall program and
I/O72.
● A
ttached Array Processor:A specialized processorwith its own internal memory and a
dedicated arithmetic unit73.
he host computer sends data and a program to the array processor, which performs the
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calculations and sends the results back74. Communicationis typically handled through a
dedicated bus75.
Q.14 Draw and explain block diagram for SIMD array processor.
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IMD (Single Instruction, Multiple Data) array processoris a system with a single control
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unit and multiple processing elements76.
The key components are:
● Control Unit:Fetches instructions and broadcaststhe same instruction to all processing
elements simultaneously77.
rocessing Elements (PE):Each PE has its own localmemory for data storage78. They all
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perform the same operation as commanded by the control unit but on their own unique
data79.
● I nterconnection Network:Provides communication paths between the processing
elements for data exchange80. This architecture ishighly efficient for tasks that involve
parallel operations on large data arrays81.
