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10N60M2

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0% found this document useful (0 votes)
46 views12 pages

10N60M2

Uploaded by

Romeo Paz Guerra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

STFH10N60M2

N-channel 600 V, 0.55 Ω typ., 7.5 A MDmesh™ M2


Power MOSFET in a TO-220FP wide creepage package
Datasheet - production data

Features
Order code VDS @ TJmax RDS(on) max ID
STFH10N60M2 650 V 0.60 Ω 7.5 A

 Extremely low gate charge


 Excellent output capacitance (COSS) profile
 100% avalanche tested
 Zener-protected
 Wide distance of 4.25 mm between the pins

Applications
 Switching applications
 LLC converters, resonant converters

Description
This device is an N-channel Power MOSFET
Figure 1: Internal schematic diagram
developed using MDmesh™ M2 technology.
D(2) Thanks to its strip layout and an improved vertical
structure, the device exhibits low on-resistance
and optimized switching characteristics,
rendering it suitable for the most demanding high
efficiency converters.

G(1)
The TO-220FP wide creepage package provides
increased surface insulation for Power MOSFETs
to prevent failure due to arcing, which can occur
in polluted environments.

S(3) AM15572v1_no_tab

Table 1: Device summary


Order code Marking Package Packing
STFH10N60M2 10N60M2 TO-220FP wide creepage Tube

May 2017 DocID029418 Rev 4 1/12


This is information on a product in full production. [Link]
Contents STFH10N60M2

Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1 Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1 TO-220FP wide creepage package information ................................ 9
5 Revision history ............................................................................ 11

2/12 DocID029418 Rev 4


STFH10N60M2 Electrical ratings

1 Electrical ratings
Table 2: Absolute maximum ratings
Symbol Parameter Value Unit
VGS Gate-source voltage ± 25 V
ID(1) Drain current (continuous) at TC = 25 °C 7.5 A
ID(1) Drain current (continuous) at TC = 100 °C 4.9 A
(1)(2)
IDM Drain current (pulsed) 30 A
PTOT Total dissipation at TC = 25 °C 25 W
(3)
dv/dt Peak diode recovery voltage slope 15 V/ns
(4)
dv/dt MOSFET dv/dt ruggedness 50 V/ns
Insulation withstand voltage (RMS) from all three leads to external
VISO 2500 V
heat sink (t = 1 s; TC = 25 °C)
Tstg Storage temperature range
- 55 to 150 °C
Tj Operating junction temperature range

Notes:
(1)Limited by package.
(2)Pulse width limited by package.
(3)I
SD ≤ 7.5 A, di/dt ≤ 400 A/µs; VDS(peak) < V(BR)DSS, VDD = 400 V
(4)V
DS ≤ 480 V

Table 3: Thermal data


Symbol Parameter Value Unit
Rthj-case Thermal resistance junction-case 5 °C/W
Rthj-amb Thermal resistance junction-ambient 62.5 °C/W

Table 4: Avalanche characteristics


Symbol Parameter Value Unit
Avalanche current, repetitive or not repetitive
IAR 1.5 A
(pulse width limited by Tjmax)
Single pulse avalanche energy
EAS 110 mJ
(starting Tj=25 °C, ID= IAR; VDD=50 V)

DocID029418 Rev 4 3/12


Electrical characteristics STFH10N60M2

2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 5: On /off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
Drain-source breakdown
V(BR)DSS VGS = 0 V, ID = 1 mA 600 V
voltage
VGS = 0 V, VDS = 600 V 1 µA
Zero gate voltage drain
IDSS VGS = 0 V, VDS = 600 V,
current 100 µA
TC=125 °C (1)
IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 µA
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2 3 4 V
Static drain-source on-
RDS(on) VGS = 10 V, ID = 3 A 0.55 0.60 Ω
resistance

Notes:
(1)Defined by design, not subject to production test.

Table 6: Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capacitance - 400 - pF
Coss Output capacitance VDS = 100 V, f = 1 MHz, - 22 - pF
VGS = 0 V
Reverse transfer
Crss - 0.84 - pF
capacitance
Coss Equivalent output
(1) VDS= 0 to 480 V, VGS= 0 V - 83 - pF
eq. capacitance
RG Intrinsic gate resistance f = 1 MHz, ID=0 A - 6.4 - Ω
Qg Total gate charge VDD = 480 V, ID = 7.5 A, - 13.5 - nC
VGS = 0 to 10 V
Qgs Gate-source charge - 2.1 - nC
(see Figure 15: "Test circuit for
Qgd Gate-drain charge gate charge behavior") - 7.2 - nC

Notes:
(1)C is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
oss eq.
increases from 0 to 80% VDSS

4/12 DocID029418 Rev 4


STFH10N60M2 Electrical characteristics
Table 7: Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time VDD = 300 V, ID = 3.75 A, - 8.8 - ns
tr Rise time RG = 4.7 Ω, VGS = 10 V - 8 - ns
(see Figure 14: "Test circuit for
td(off) Turn-off delay time resistive load switching times" - 32.5 - ns
and Figure 19: "Switching time
tf Fall time waveform") - 13.2 - ns

Table 8: Source drain diode


Symbol Parameter Test conditions Min. Typ. Max. Unit
ISD(1) Source-drain current - 7.5 A
Source-drain current
ISDM(1)(2) - 30 A
(pulsed)
VSD(3) Forward on voltage ISD = 7.5 A, VGS = 0 V - 1.6 V
trr Reverse recovery time ISD = 7.5 A, di/dt = 100 A/µs - 270 ns
Qrr Reverse recovery charge VDD = 60 V - 2 µC
(see Figure 16: "Test circuit for
IRRM Reverse recovery current inductive load switching and - 14.4 A
diode recovery times")
trr Reverse recovery time ISD = 7.5 A, di/dt = 100 A/µs - 376 ns
Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 2.8 µC
(see Figure 16: "Test circuit for
IRRM Reverse recovery current inductive load switching and - 15 A
diode recovery times")

Notes:
(1)Limited by package.
(2)Pulse width limited by safe operating area.
(3)Pulsed: pulse duration = 300 µs, duty cycle 1.5%.

DocID029418 Rev 4 5/12


Electrical characteristics STFH10N60M2
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area Figure 3: Thermal impedance

Figure 4: Output characteristics Figure 5: Transfer characteristics

Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance


VGS VDS
(V) (V)
12 VDS VDD=480V
ID=7.5A 500
10
400
8
300
6
200
4

100
2

0 0
0 2 4 6 8 10 12 Qg(nC)

6/12 DocID029418 Rev 4


STFH10N60M2 Electrical characteristics
Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs.
temperature
GADG070620161454FSR
C
(pF)
ID=250 µA
1000
Ciss

100

Coss
10

1 Crss

0.1
0.1 1 10 100 VDS(V)

Figure 10: Normalized on-resistance vs temperature Figure 11: Source-drain diode forward
characteristics

ID=3 A

Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Output capacitance stored energy
GADG070620161505FSR
Eoss(µJ)

0
0 100 200 300 400 500 600 VDS(V)

DocID029418 Rev 4 7/12


Test circuits STFH10N60M2

3 Test circuits
Figure 14: Test circuit for resistive load Figure 15: Test circuit for gate charge
switching times behavior

Figure 16: Test circuit for inductive load Figure 17: Unclamped inductive load test
switching and diode recovery times circuit

Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform

8/12 DocID029418 Rev 4


STFH10N60M2 Package information

4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: [Link].
ECOPACK® is an ST trademark.

4.1 TO-220FP wide creepage package information


Figure 20: TO-220FP wide creepage package outline

DM00260252_1

DocID029418 Rev 4 9/12


Package information STFH10N60M2
Table 9: TO-220FP wide creepage package mechanical data
mm
Dim.
Min. Typ. Max.
A 4.60 4.70 4.80
B 2.50 2.60 2.70
D 2.49 2.59 2.69
E 0.46 0.59
F 0.76 0.89
F1 0.96 1.25
F2 1.11 1.40
G 8.40 8.50 8.60
G1 4.15 4.25 4.35
H 10.90 11.00 11.10
L2 15.25 15.40 15.55
L3 28.70 29.00 29.30
L4 10.00 10.20 10.40
L5 2.55 2.70 2.85
L6 16.00 16.10 16.20
L7 9.05 9.15 9.25
Dia 3.00 3.10 3.20

10/12 DocID029418 Rev 4


STFH10N60M2 Revision history

5 Revision history
Table 10: Document revision history
Date Revision Changes
07-Jun-2016 1 First release.
Document status promoted from preliminary data to production
16-Jun-2016 2 data.
Minor text changes.
Modified: title and RDS(on) in cover page
18-Aug-2016 3 Modified: Table 5: "On /off states" and Table 7: "Switching times"
Minor text changes
Modified features on cover page.
Modified Table 2: "Absolute maximum ratings" and Table 4:
08-May-2017 4
"Avalanche characteristics".
Minor text changes.

DocID029418 Rev 4 11/12


STFH10N60M2

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STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2017 STMicroelectronics – All rights reserved

12/12 DocID029418 Rev 4

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