IRFP4668PbF

VDSS 200V
RDS(on) typ. 8.0m
max. 9.7m
ID 130A

TO-247AC

Applications
• High Efficiency Synchronous Rectification in SMPS
• Uninterruptible Power Supply
• High Speed Power Switching
• Hard Switched and High Frequency Circuits

Benefits
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
• Fully Characterized Capacitance and Avalanche SOA
• Enhanced body diode dV/dt and dI/dt Capability
• Lead-Free

Base Part Number Package Type Standard Pack Orderable Part Number
Form Quantity
IRFP4668PbF TO-247AC Tube 25 IRFP4668PbF

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 130
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 92 A
IDM Pulsed Drain Current  520
PD @TC = 25°C Maximum Power Dissipation 520 W
Linear Derating Factor 3.5 W/°C
VGS Gate-to-Source Voltage ± 30 V
dv/dt Peak Diode Recovery  57 V/ns
TJ Operating Junction and
-55 to + 175
TSTG Storage Temperature Range
°C
Soldering Temperature, for 10 seconds
300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw 10lbfin (1.1Nm)
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy  760 mJ
IAR Avalanche Current  A
See Fig. 14, 15, 22a, 22b
EAR Repetitive Avalanche Energy  mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case  ––– 0.29
RCS Case-to-Sink, Flat Greased Surface 0.24 ––– °C/W
RJA Junction-to-Ambient ––– 40

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Static @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 200 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.21 ––– V/°C Reference to 25°C, ID = 5mA
RDS(on) Static Drain-to-Source On-Resistance ––– 8.0 9.7 m VGS = 10V, ID = 81A 
VGS(th) Gate Threshold Voltage 3.0 ––– 5.0 V VDS = VGS, ID = 250µA
––– ––– 20 VDS = 200V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 200V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
RG Internal Gate Resistance ––– 1.0 ––– 
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 150 ––– ––– S VDS = 50V, ID = 81A
Qg Total Gate Charge ––– 161 241 ID = 81A
Qgs Gate-to-Source Charge ––– 54 ––– VDS =100V
nC
Qgd Gate-to-Drain ("Miller") Charge ––– 52 ––– VGS = 10V 
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 109 ––– ID = 81A, VDS =0V, VGS = 10V
td(on) Turn-On Delay Time ––– 41 ––– VDD = 130V
tr Rise Time ––– 105 ––– ID = 81A
ns
td(off) Turn-Off Delay Time ––– 64 ––– RG = 2.7
tf Fall Time ––– 74 ––– VGS = 10V 
Ciss Input Capacitance ––– 10720 ––– VGS = 0V
Coss Output Capacitance ––– 810 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 160 ––– ƒ = 1.0 MHz, See Fig. 5
Coss eff. (ER) Effective Output Capacitance pF VGS = 0V, VDS = 0V to 160V 
––– 630 –––
(Energy Related) 
Coss eff. (TR) Effective Output Capacitance VGS = 0V, VDS = 0V to 160V 
––– 790 –––
(Time Related)
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current MOSFET symbol D

––– ––– 130 A

(Body Diode) showing the
ISM Pulsed Source Current integral reverse G

––– ––– 520 A

(Body Diode)  p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 81A, VGS = 0V 
trr Reverse Recovery Time ––– 130 ––– TJ = 25°C
ns VR = 100V,
––– 155 ––– TJ = 125°C
IF = 81A
Qrr Reverse Recovery Charge ––– 633 ––– TJ = 25°C di/dt = 100A/µs 
nC
––– 944 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 8.7 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by max. Junction temperature.
 Limited by TJmax, starting TJ = 25°C, L = 0.23mH, RG = 25, IAS = 81A, VGS =10V. Part not recommended for use above this value.
 ISD ≤ 81A, di/dt ≤ 520A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
 Pulse width ≤ 400µs; duty cycle ≤ 2%.
 Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while V DS is rising from 0 to 80% VDSS.
 Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while V DS is rising from 0 to 80% VDSS.
 When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques.
 R is measured at TJ approximately 90°C.

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Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage

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Fig 7. Typical Source-to-Drain Diode

Forward Voltage Fig 8. Maximum Safe Operating Area

Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Drain-to-Source Breakdown Voltage

Fig 11. Typical Coss Stored Energy Fig 12. Maximum Avalanche Energy vs. Drain Current

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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 14. Typical Avalanche Current vs. Pulsewidth

Notes on Repetitive Avalanche Curves , Figures 14, 15:

(For further info, see AN-1005 at [Link])
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature
far in excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)

PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC

Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature

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Fig. 16 Threshold Voltage vs. Temperature Fig. 17 Typical Recovery Current vs. dif/dt

Fig 18. Typical Recovery Current vs. dif/dt Fig 19. Typical Stored Charge vs. dif/dt

Fig 20. Typical Stored Charge vs. dif/dt

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Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs

Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms

Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform

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TO-247AC Package Outline (Dimensions are

TO-247AC Part Marking Information

TO-247AC package is not recommended for Surface Mount Application.

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Revision History
Date Rev. Comments
• Changed datasheet to Infineon format
12/02/2021 2.1 • Corrected 10ms and 1ms labels of Fig.8_SOA curve
• Added disclaimer on last page.

10/30/2024 2.2 • Updated Part marking –page 8

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Due to technical requirements products may contain dangerous substances. For information on the types in question please
contact your nearest Infineon Technologies office.
The Infineon Technologies component described in this Data Sheet may be used in life support devices or systems and or
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failure of such components can reasonably be expected to cause the failure of that life support, automotive, aviation and
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