Computer

Architecture
Dr. Haitham Farouk
Dr. Muhamed Abdulhadi
Assistant Professor
Computer Science Department

Lecture 2
 • Block Diagram of a Computer
• What is the Central Processing Unit (CPU)?
Central
• Von Neumann Architecture
Processing • Harvard Architecture

Unit • Instruction Execution Steps

• Design Principles for Modern Computers
(CPU) • Instruction-Level Parallelism
• The History of the CPU

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Hardware Architecture vs. Programming Model
• Hardware architecture defines the physical structure of the
computer’s components and their connections, while the
• Programming model provides a conceptual framework for
interacting with this hardware.
The programming model involves:
Instruction Set Architecture (ISA): The set of commands understood by
the CPU, which acts as a bridge between high-level code and the
hardware.
Assembly Language: A low-level language that maps directly to the
machine code of the CPU.
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 Block Diagram of a Computer

❑ Processor: The brain that executes instructions

from the software program.
❑ Storage: Stores data and instructions.
▪ The means of containing primary memory (main memory),
which is the computer’s working memory and major
operational component;

▪ Primary storage: The CPU has its own very fast, limited-
capacity storage components that hold data and
instructions temporarily while processing. This includes
Registers, Cash Memory, RAM, ROM.

▪ Secondary storage: Secondary storage, or auxiliary

storage, is a type of non-volatile memory that provides
long-term, cost-effective storage for data, applications, and
operating systems. This includes hard disk drives (HDDs),
solid-state drives (SSDs), USB flash drives, and optical discs
like DVDs and CDs.
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Block Diagram of a Computer (cont.)

❑ Input/Output Devices: Facilitates interaction

with the outside world. Input devices enter data
into a computer system, such as a keyboard,
mouse, microphone, and scanner. Output devices
display information from a computer, including a
monitor, printer, speakers, and headphones. Some
devices, like touchscreens and headsets, can
function as both.

❑ Buses: Electronic communication pathways that

connect various components like the CPU, memory,
and peripherals, allowing them to transfer data,
addresses, and control signals. (a bundle of wires
that carry signals and power between different
components.)

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 What is the Central Processing Unit (CPU)?

❑ CPU: simply called Processor

▪ The CPU, often called the "brain" & “active part” of the
computer, is the primary hardware component, which does
all the work of data manipulation and decision making.
▪ Executes instructions from software programs.
▪ Interprets and carries out the basic operations of a
computer system by performing the fetch-decode-execute
cycle on machine code instructions.
▪ Performs calculations, manages data flow, and coordinates
all operations within the computer system.
▪ Coordinates interactions with memory and peripherals to
run software efficiently.
▪ Modern CPUs are microprocessors (integrated circuit (IC))
containing billions of transistors on a single silicon chip.

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Key Functions of a CPU

❑ Processing Instructions: Executes arithmetic,

logic, control, and input/output operations.

❑ Data Management: Moves data between

memory/storage and processing units.

❑ Control Flow: Directs operations of the

Arithmetic Logic Unit (ALU), memory, and
peripherals (e.g., signals I/O devices to activate).

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Key Components of a CPU

A CPU contains two main components: datapath

and control (the respective brawn (worker) and
brain (manager) of the CPU).

▪ Datapath: is the hardware that performs all the

required operations, for example, ALU,
registers, and internal buses.

▪ Control: is the hardware that tells the datapath

what to do, in terms of switching, operation
selection, data movement between ALU
components, etc.

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 Key Components of a CPU (cont.)
Component Description Function
Directs data flow, coordinates operations by generating Orchestrates the overall flow of data and
Control Unit control signals to fetch, decode, and execute instructions. instructions within the CPU and between
(CU) Manages the instruction pipeline and synchronizes with other the CPU and external devices (manages
hardware. fetch-decode-execute cycle timing).

Specialized circuitry for performing arithmetic (+, –, ×, ÷) (e.g.,

Arithmetic Logic Handles math operations and evaluate
5+3) and logical operations (comparison AND/OR/NOT logic
Unit (ALU) conditions for programs.
gates) (e.g., ‘if x > y’).
Small, ultra-fast storage locations inside the CPU (e.g.,
Provide immediate access to data for
program counter, accumulator, general-purpose registers).
Registers quick operations, reducing reliance on
They hold temporary data, addresses, or intermediate results slower main memory.
during processing.
Reduces latency by keeping data closer
High-speed, on-chip memory (L1, L2, L3 levels) that stores
Cache Memory to the processor, improving performance
frequently used data and instructions. over main memory access.
Enables communication and data
Pathways like address bus for memory locations, data bus for
Bus Interface transfer across the system. Facilitates
transferring information, and control bus for signals. Connects
(System Buses) communication with RAM, storage, and
CPU to RAM and I/O devices via data/address buses. I/O devices. 9
Primary Storage

Primary Storage consists of several distinct types, each with specific

characteristics and roles:

▪ Registers: is the smallest and fastest form (memory) of primary storage, integrated
within the CPU, used for storing temporary data/results and certain control
information during instruction execution.
▪ Cache Memory: is organized in a multi-level hierarchy (L1, L2, …), serves as a buffer
between the CPU and main memory, reducing latency and improving performance by
storing frequently accessed data.
▪ Read-only memory (ROM): is a non-volatile type of primary storage. ROM retains its
contents even when power is removed, making it suitable for storing programs and
data that need not be altered.

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Primary Storage (cont.)

▪ Random Access Memory (RAM): is a volatile memory used to hold instructions

and data of currently running programs. RAM is divided into static RAM (SRAM) and
dynamic RAM (DRAM). SRAM is faster and does not require refreshing, while DRAM
is slower, offers higher density, and requires periodic refreshing.

Except for ROM, primary storage components such as registers, cache, and RAM are
volatile, meaning they lose their contents when power is turned off, which has
implications for data persistence.

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Von Neumann Architecture
▪ The von Neumann architecture is a
foundational computer design model
proposed by mathematician John von
Neumann in 1945 (based on earlier
work by Alan Turing) for virtually all
modern computers.
▪ It revolutionized computing by
CPU
introducing the concept of a stored-
program computer, where both
ALU
instructions (program code) and data
are stored (reside) in the same
addressable memory space, accessed
via a single bus for fetching and
Memory Control I/O devices
processing.
▪ This allows the computer to treat
instructions as modifiable data,
enabling flexible programming and
self-modification. 12
Von Neumann Architecture: Key Features
The core features of the von Neumann model include:
• Stored-Program Concept: Programs are stored
in memory as binary code, just like data.
CPU
Instructions and data share the same memory,
blurring the line between software and hardware. ALU
• Single Bus System: A unified pathway connects
the CPU to Memory and I/O through System
Buses, simplifying design but creating potential Memory Control I/O devices
bottlenecks (the "von Neumann bottleneck").
• Sequential Execution: The CPU operates in a
fetch-decode-execute cycle. Instructions are
processed one at a time in order, though modern
optimizations allow parallelism.
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Von Neumann Architecture: Key Components and their Roles
Component Description Role
Contains ALU for computations, Control Unit
Central Processing Fetches, decodes, and executes
for orchestration, and registers for temporary
Unit (CPU) instructions from memory.
storage.

Holds active programs and

Main Memory Unified storage for both program instructions
operands; accessed via
(RAM) and data; volatile and random-access.
addresses.

Peripherals like keyboards, displays, or Allows data exchange with the

Input/Output (I/O)
storage drives; connected via buses or external world (e.g., loading
Devices
controllers. programs).

Address bus (specifies memory locations), Facilitates communication

Buses
data bus (transfers info), control bus (signals). between CPU, memory, and I/O.

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Von Neumann Architecture Bottleneck
The architecture's major limitation is the shared bus/memory for instructions
and data:

▪ Only one operation (read or write) can occur per clock cycle.
▪ This creates a performance bottleneck because the CPU often waits for
data/instructions to traverse the bus.

Modern Mitigations:
▪ Caches: On-chip L1/L2 caches store recent data/instructions.
▪ Pipelining: Overlaps stages of multiple instructions.
▪ Parallelism: Multi-core CPUs execute tasks simultaneously.

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Harvard Architecture
▪ An earlier computer design
model, where program
instructions and data are CPU
stored in separate memory
units that are accessed
ALU
through independent
buses.
Data
Instruction
▪ This separation allows the memory Control memory
processor to fetch
instructions and access
data simultaneously, which
helps avoid the bottleneck
present in traditional Von
I/O devices
Neumann systems.
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Von Neumann Architecture vs. Harvard Architecture
Feature Von Neumann Architecture Harvard Architecture
Single memory space for instructions and Separate memories (one for code, one for
Memory Structure
data data)

Bus Usage Shared bus; potential bottleneck Dual/parallel buses; faster parallel access

Slower for simultaneous instruction/data

Access Speed Faster, as fetches can overlap
fetch
Complexity/Cost Simpler and cheaper to implement More complex and expensive

General-purpose computers (e.g., x86 Embedded systems, DSPs, microcontrollers

Use Cases
PCs) (e.g., some ARM variants)
Limited self-modification; better for real-
Flexibility High; programs can treat code as data
time tasks

Modern systems often use a "modified Harvard" approach (e.g., separate instruction/data caches but
unified main memory) to balance benefits.
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Instruction Execution Steps: The fetch-decode-execute cycle

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Instruction Execution Steps: The fetch-decode-execute cycle

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Instruction Execution Steps: The fetch-decode-execute cycle (cont.)
The four main stages of the (Computer) Machine Cycle, also known as the Instruction Cycle
or Fetch-Decode-Execute-Store cycle, which describes how a CPU processes instructions.

1. Fetch
▪ Description: The Control Unit (CU) retrieves the next instruction from memory,
specifically from the address pointed to by the Program Counter (PC).
▪ Components involved: Control Unit, Memory, Registers (Program Counter).

2. Decode
▪ Description: The fetched instruction is interpreted by the Control Unit to determine
the operation to be performed and identify any required operands (data).
▪ Components involved: Control Unit, Registers (Instruction Register).
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Instruction Execution Steps: The fetch-decode-execute cycle (cont.)
3. Execute
▪ Description: The Arithmetic Logic Unit (ALU) performs the operation specified by the
decoded instruction, using the necessary data.
▪ Components involved: ALU, Control Unit, Registers.

4. Store
▪ Description: The results of the execution are stored back into memory or registers for
later use.
▪ Components involved: Control Unit, Memory, Registers.

➢ Note: The instruction and execution phases together make up one machine cycle.
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Design Principles for Modern Computers

▪ All instructions directly executed by hardware (no microinstructions)

▪ Maximize rate at which instructions are issued (start as many
instructions per second as possible).
▪ Instructions should be easy to decode.
▪ Only loads, stores should reference memory (other instructions should
operate only on registers).
▪ Provide great number of registers (since accessing memory is relatively
slow).

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Instruction-Level Parallelism

▪ Fetching of instructions from memory is a major bottleneck in

instruction execution speed.
▪ Reduce this problem by, stored these instructions in a set of registers
called the prefetch buffer.
▪ prefetching divides instruction execution up into two parts, fetching and
actual execution.
▪ Instead of dividing instruction execution into only two parts, it is often
divided into many parts, each one handled by a dedicated piece of
hardware, all of which can run in parallel.

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The Processor (CPU): History

Intel 4004 Die

▪ Introduced in 1970

▪ The first ever microprocessor

▪ 2,250 transistors

▪ 12 𝐦𝐦𝟐

▪ 108 KHz

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The Processor (CPU): History (cont.)

Intel 8086 Die Scan

▪ Introduced in 1979

▪ Basi architecture of the IA32PC

▪ 29,000 transistors

▪ 33 𝐦𝐦𝟐

▪ 5 MHz

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The Processor (CPU): History (cont.)

Intel 80486 Die Scan

▪ Introduced in 1989

▪ 1st pipeline implementation of IA32

▪ 1,200,000 transistors

▪ 81 𝐦𝐦𝟐

▪ 25 MHz

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The Processor (CPU): History (cont.)

Intel Pentium Die Photo

▪ Introduced in 1993

▪ 1st superscalar implementation of IA32

▪ 3,100,000 transistors

▪ 296 𝐦𝐦𝟐

▪ 60 MHz

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The Processor (CPU): History (cont.)

Pentium III
▪ Introduced in 1999

▪ 9,500,000 transistors

▪ 125 𝐦𝐦𝟐

▪ 450 MHz

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The Processor (CPU): History (cont.)

Pentium 4
▪ Introduced in 2000

▪ 55,000,000 transistors

▪ 146 𝐦𝐦𝟐

▪ 3 GHz

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The Processor (CPU): Multi-Core Processors

AMD Barcelona Intel Core i5 Intel Core i7 IBM POWER 8

Intel Core i3
4 cores 8 cores 8 cores

Nvidia Fermi Intel SCC Intel Xeon phi Tilera TILE Gx

448 “cores” networked (48 (50 cores) Tilera (72cores) 100 cores, networked
cores)
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References:

• Basic Computer Architecture. (13.8, )

• Computer Organization and Design. 3rd edition (1.3, )
• Computer Organization and Architecture. 11th edition (16.1, 16.3)
• The Architecture of Computer Hardware, Systems Software, & Networking. 5th edition (7.0, 7.1)
• https://www.sciencedirect.com/topics/computer-science/primary-storage
• https://www.ibm.com/think/topics/primary-storage & https://www.ibm.com/think/topics/primary-vs-secondary-storage

The End