Xilinx Tool Flow
This material exempt per Department of Commerce license exception TSU
2011 Xilinx, Inc. All Rights Reserved
Objectives
After completing this module, you will be able to:
List the steps of the Xilinx design process
Implement and simulate an FPGA design by using default software
options
Tool Flow 2
2011 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
Overview
ISE Foundation
Summary
Lab 1: Xilinx Tool Flow Demo
Tool Flow 3
2011 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Xilinx Design Flow
Plan & Budget
Create Code/
Schematic
HDL RTL
Simulation
Implement
Translate
Functional
Simulation
Synthesize
to create netlist
Map
Place & Route
Attain Timing
Closure
Timing
Simulation
Generate
BIT File
Configure
FPGA
Tool Flow 4
2011 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Design Entry
Create designs in HDL or Schematic
Plan and budget
Whichever method you use, you will need a tool to generate an
EDIF or NGC netlist to bring into the Xilinx implementation tools
Popular synthesis tools include: Synplify, Precision, FPGA Compiler II, and XST
Tools available to assist in design entry
Architecture Wizard, CORE Generator system, and StateCAD tools
Simulate the design to ensure that it works as expected!
Plan & Budget
Create Code/
Schematic
...
Functional
Simulation
HDL RTL
Simulation
Synthesize
to create netlist
Tool Flow 5
2011 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Synthesis
Generate a netlist file
After coding up your HDL code, you will need a
tool to generate a netlist (NGC or EDIF)
Xilinx Synthesis Tool (XST) included
Support for Popular Third Party Synthesis tools: Synplify and
Synplify Pro from Synplicity, and Precision from Mentor
Graphics
Tool Flow 6
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For Academic Use Only
Implementation
Process a netlist file
Consists of three phases
Translate: Merge multiple design files
into a single netlist
Map: Group logical symbols from the
netlist (gates) into physical components
(slices and IOBs)
Place & Route: Place components onto
the chip, connect the components, and
extract timing data into reports
Access Xilinx reports and tools at
each phase
Timing Analyzer, Floorplanner, FPGA
Editor, XPower
Netlist Generated
From Synthesis
.
.
.
Implement
Translate
Map
Place & Route
.
.
.
Tool Flow 7
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For Academic Use Only
...
Configuration
Testing and Verification
Once a design is implemented, you must create a file that the
FPGA can understand
This file is called a bitstream: a BIT file (.bit extension)
The BIT file can be downloaded
Directly into the FPGA
Use a download cable such as Platform USB
To external memory device such as a Xilinx Platform Flash PROM
Must first be converted into a PROM file
Tool Flow 8
2011 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Online Software Manuals
See Development System Reference Guide for Flow Diagrams
Tool Flow 9
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For Academic Use Only
Timing Closure
Tool Flow 10
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Outline
Overview
ISE Foundation
Summary
Lab 1: Xilinx Tool Flow
Demo
Tool Flow 11
2011 Xilinx, Inc. All Rights Reserved
For Academic Use Only
ISE Project Navigator
Xilinx ISE Foundation is built around the Xilinx Design Flow
Enter Designs
Access to synthesis tools
Including third-party
synthesis tools
Implement your design
with a simple double-click
Fine-tune with easy-toaccess software options
Download
Generate a bitstream
Configure FPGA using
iMPACT
Tool Flow 12
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For Academic Use Only
Entering Designs
Source Wizard available to assist with design entry
Select source type
Design Entry Methods
Schematic
HDL source (VHDL and
Verilog)
Design Entry Tools
Architecture Wizard
BMM/MEM/UCF Files
Core Generator
ChipScope
Embedded Processor
System Generator
Simulation Test Bench
VHDL
Verilog
Tool Flow 13
2011 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Synthesizing Designs
Generate a netlist file using XST (Xilinx Synthesis Technology)
Synthesis Processes and
Analysis
Access report
View Schematics (RTL or
Technology)
Check Syntax
Generate Post-Synthesis
Simulation Model
Highlight HDL
Sources
Double-click to
Synthesize
Tool Flow 14
2011 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Implementing Designs
Process netlist generated from synthesis
Implement a design
1
Translate
Highlight HDL
Sources
Access reports
Post-Translate Simulation Model
Map
Access reports
Post-Map Static Timing
Manually place components
Post-Map Simulation Model
Double-click to
Implement
Place & Route
Access reports
Analyze timing/Floorplan (PlanAhead)
Manually place & route components
And more
Tool Flow 15
2011 Xilinx, Inc. All Rights Reserved
For Academic Use Only
The Design Summary
Displays Design Data
Quick View of
Reports,
Constraints
Project Status
Device Utilization
Detailed Reports
Design Properties
Performance
Summary (not
shown)
Tool Flow 16
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Simulating Designs
Verify the design with the ISE Simulator
2
Add a test bench
Select simulation type
Select simulation
VHDL, Verilog, or Xilinx waveform file
Perform a Behavioral Simulation
Use UNISIM/UniMacro library when FPGA
primitives are instantiated in the design
Use XilinxCoreLib library when IP cores are
instantiated in the design
Perform a timing simulation
Use Xilinx SIMPRIM library when FPGA
primitives are instantiated in the design
Highlight test
bench
SmartModels
Simulation library for both functional and
timing simulation of Xilinx Hard-IP such as
PPC, PCIe, GT, TEMAC are used in the
design
Double-click to
simulate
Tool Flow 17
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For Academic Use Only
Configuring FPGAs
Generate PROM files and download to devices using iMPACT
Configure FPGAs from computer
Use iMPACT to download bitstream from
computer to FPGA via Xilinx download cable
(ie. Platform USB)
Highlight source file
Configure FPGAs from External Memory
2
Xilinx Platform Flash
Use iMPACT to generate PROM file and
download to PROM using Xilinx download cable
Double-click to
generate .bit
Generic Parallel PROM
Use iMPACT to generate PROM file - no
support for programming
Compact Flash (Xilinx System ACE required)
Use iMPACT to generate SysACE file - no
support for programming
Double-click to invoke
iMPACT programming tools
Tool Flow 18
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For Academic Use Only
Outline
Overview
ISE
Summary
Lab 1: Xilinx Tool Flow
Tool Flow 19
2011 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Review Questions
What are the phases of the Xilinx design flow?
What are the components of implementation, and what
happens at each step?
What are two methods of programming an FPGA?
Tool Flow 20
2011 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Answers
What are the phases of the Xilinx design flow?
Plan and budget, create code or schematic, RTL simulation, synthesize,
functional simulation, implement, timing closure, timing simulation, and BIT file
creation
What are the components of implementation, and what happens at
each step?
Translate: merges multiple design files into one netlist
Map: groups logical symbols into physical components
Place & Route: places components onto the chip and connects them
What are two methods of programming an FPGA?
Directly from Computer
From external memory device
Tool Flow 21
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For Academic Use Only
Summary
Implementation means more than Place & Route
Xilinx provides a simple pushbutton tool to guide you
through the Xilinx design process
Tool Flow 22
2011 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
Overview
ISE
Summary
Lab 1: Xilinx Tool Flow
Tool Flow 23
2011 Xilinx, Inc. All Rights Reserved
For Academic Use Only
