Introduction to VLSI Circuits and
Systems
Chapter 02
Logic Design with MOSFETs
Dept. of Electronic Engineering
National Chin-Yi University of Technology
Fall 2007
Introduction to VLSI Circuits and Systems, NCUT
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
Introduction to VLSI Circuits and Systems, NCUT
p-n Junction
A junction between p-type and n-type semiconductor forms a diode
Current flows only in one direction
anode
cathode
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nMOS Transistor
Four terminals: gate (G), source (S), drain (D), body (B)
Gateoxidebody stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal oxide semiconductor (MOS) capacitor
Even though gate is no longer made of metal
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nMOS Operation (1/2)
Body is usually tied to ground (0 V)
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
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nMOS Operation (2/2)
When the gate is at a high voltage
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from source through channel to drain,
transistor is ON
Introduction to VLSI Circuits and Systems, NCUT
pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
Introduction to VLSI Circuits and Systems, NCUT
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
Introduction to VLSI Circuits and Systems, NCUT
Ideal Switches (1/3)
CMOS integrated circuits use bi-directional devices called MOSFETs as
logic switches
Controlled switches, e.g, assert-high and assert-low switches
An assert-high switch is showing in Figure 2.1
(a) Open
(b) Closed
Figure 2.1 Behavior of an assert-high switch
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Ideal Switches (2/3)
g = (a 1) b = (a 1)
Figure 2.2 Series-connected switches
g = (a 1) + (b 1) = a +
Figure 2.4 Parallel-connected switches
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Ideal Switches (3/3)
(a) Closed
Figure 2.6 Series-connected complementary switches
(b) Open
Figure 2.5 An assert-low switch
Figure 2.7 An assert-low switch
Figure 2.8 A MUXbased NOT gate
Introduction to VLSI Circuits and Systems, NCUT
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
Introduction to VLSI Circuits and Systems, NCUT
MOSFET as Switches
MOSFET: Metal-Oxide-Semiconductor Field-Effect
Transistor
nFET: an n-channel MOSFET that uses negatively
charged electrons for electrical current flow
pFET: a p-channel MOSFET that uses positive
charges for current flow
In many ways, MOSFETs behave like the idealized
switches introduced in the previous section
The voltage applied to the gate determines the
current flow between the source and drain terminals
(a) nFET symbol
(b) pFET symbol
Figure 2.9 Symbols
used for nFETs and
pFETs
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MOSFET as Switches
Early generations of silicon MOS logic
circuits used both positive and negative
supply voltages as Figure 2.10 showing
In modern designs require only a single
positive voltage VDD and the ground
connection, e.g. VDD = 5 V and 3.3 V or
lower
Figure 2.10 Dual power supply
voltages
The relationship between logic variables
x and its voltages Vx
0 V x VDD
x 0 means that V x 0V
x 1 means that V x V DD
(2.14)
(2.15)
(a) Power supply
(b) Logic
connection
definitions
Figure 2.11 Single voltage power supply
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Switching Characteristics of MOSFET
In general,
Low voltages correspond to logic 0 values
High voltages correspond to logic 1 values
The transition region between the highest
logic 0 voltage and the lowest logic 1
voltage is undefined
nFET
y x A which is valid iff A 1
(a) Open
(b) Closed
Figure 2.12 nFET switching
characteristics
(2.16)
pFET
y x A which is valid iff A 0
(2.17)
(a) Open
(b) Closed
Figure 2.13 pFET switching
characteristics
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nMOS FET Threshold Voltages
An nFET is characterized by a threshold voltage
VTn that is positive, typical is around VTn = 0.5 V
to 0.7 V
If VGSn VTn , then the transistor acts like an open
(off) circuit and there is no current flow between
the drain and source
If VGSn VTn , then the nFET drain and source are
connected and the equivalent switch is closed
(on)
Thus, to define the voltage VA that is associated
with the binary
A (2.20)
V variable
V
A
GSn
(a) Gate-source
voltage
(b) Logic
translation
Figure 2.14 Threshold voltage of an
nFET
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pMOS FET Threshold Voltages
An pFET is characterized by a threshold voltage
VTp that is negative, typical is around VTp = 0.5
V to 0.8 V
If VSGp VTp
, then the transistor acts like an open
(off) switch and there is no current flow between the
drain and source
If
VSGp VTp
, then the pFET drain and source are
connected and the equivalent switch is closed (on)
(a) Source-gate
voltage
Thus, to the applied voltage VA we first sum
voltage to write
V A VSGp V DD
(2.23)
VA 0 V
V A VDD VSGp
(2.24)
V A VDD
V DD VTp
(2.25)
Note that the transition
between a logic 0 and a logic
(2.26)
(b) Logic
translation
Figure 2.15 pFET threshold voltage
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nFET Pass Characteristics
An ideal electrical switch can pass any voltage
applied to it
As Figure 2.16(b), the output voltage Vy is
reduced to a value
V1 V DD VTn
(2.27)
since
VGSn VTn
(a) Logic 0 transfer
Which is less than the input voltage VDD, called
threshold voltage loss
Thus, we say that the nFET can only pass a weak
logic 1; in other word, the nFET is said to pass a
strong logic 0 can pass a voltage in the range
[0, V1]
(b) Logic 1 transfer
Figure 2.16 nFET pass
characteristics
Introduction to VLSI Circuits and Systems, NCUT
pFET Pass Characteristics
Figure 2.17(a) portrays the case where Vx =
VDD corresponding to a logic 1 input. The
output voltage is
V y V DD
Figure 2.17(b), the transmitted voltage can
only drop to a minimum value of
V y VTp
(2.29),which is an ideal logic 1 level
(2.30)
since
(a) Logic 0 transfer
VSGp VTp
The results of the above discussion
nFETs pass strong logic 0 voltages, but weak
logic 1 values
pFETs pass strong logic 1 voltages, but weak
logic 0 levels
Use pFETs to pass logic 1 voltages of VDD
Use nFETs to pass logic 0 voltages of VSS = 0 V
(b) Logic 1 transfer
Figure 2.17 pFET pass
characteristics
Introduction to VLSI Circuits and Systems, NCUT
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
Introduction to VLSI Circuits and Systems, NCUT
Basic Logic Gates in CMOS
Digital logic circuits are nonlinear networks that
use transistors as electronic switches to divert one
of the supply voltages VDD or 0 V to the output
The general switching network
(a) f = 1
output
Figure 2.18 General CMOS logic
gate
(b) f = 0
output
Figure 2.19 Operation of a CMOS logic
gate
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The NOT Gate (1/2)
Figure 2.20 A complementary
pair
(a) x = 0 input
(a) Logic symbol
(b) x = 1 input
(b) Truth Table
Figure 2.21 Operation
of the complementary
pair
Figure 2.22 NOT
gate
Introduction to VLSI Circuits and Systems, NCUT
The NOT Gate (2/2)
(a) x = 0 input
Figure 2.23 CMOS not gate
(b) x = 1 input
Figure 2.24 Operation of
the CMOS NOT gate
Introduction to VLSI Circuits and Systems, NCUT
The NOR Gate (1/2)
(a) Logic symbol
(a) Logic diagram
(b) Voltage network
(b) Truth Table
Figure 2.25 NOR logic gate
Figure 2.26 NOR2
using a 4:1
multiplexor
Figure 2.27 NOR2
gate Karnaugh map
Introduction to VLSI Circuits and Systems, NCUT
NOR (2/2)
Figure 2.28 NOR2 in CMOS
Figure 2.30 NOR3 in
CMOS
Figure 2.29 Operational summary of the
NOR2 gate
Introduction to VLSI Circuits and Systems, NCUT
NAND (1/2)
(a) Logic symbol
(a) Logic diagram
Figure 2.33 NAND2 K-map
(b) Truth Table
Figure 2.31 NAND2 logic
gate
(b) Voltage network
Figure 2.32 NAND2
using 4:1 multiplexor
Introduction to VLSI Circuits and Systems, NCUT
NAND (2/2)
Figure 2.34 CMOS NAND2 logic
circuit
Figure 2.36 NAND3 in CMOS
Figure 2.35 Operational summary of the NAND2
gate
Introduction to VLSI Circuits and Systems, NCUT
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
Introduction to VLSI Circuits and Systems, NCUT
Complex Logic Gate (1/3)
Complex or combinational logic gates
Useful in VLSI system-level design
Consider a Boolean expression F (a, b, c ) a (b c)
F (a, b, c) a (b c)
a (b c)
(2.50)
[a (b c)] 1
Expanding by simply ANDing the result with a logical 1
F a 1 (b c) 1
(2.51)
Introduction to VLSI Circuits and Systems, NCUT
Complex Logic Gate (2/3)
nFET array that
gives F=0 when
necessary
Figure 2.37 Logic function example
Figure 2.39 nFET circuit for F
F a 1 (b c) 1
Figure 2.38 pFET circuit for
F function from equation
(2.51)
Figure 2.40 Karnaugh for nFET
circuit
Introduction to VLSI Circuits and Systems, NCUT
Complex Logic Gate (3/3)
The characteristics of Complementary CMOS
CMOS
0 ~ VDD (full swing) VDD
~ 0 ( ) 0 VDD
CMOS
(function)
(mass production)
(reliability)
(variation corners)
(specifications)
(margin)
Figure 2.41 Finished
complex CMOS logic gate
circuit
Introduction to VLSI Circuits and Systems, NCUT
Structured Logic Design
(1/4)
CMOS logic gates are intrinsically inverting
Output always produces a NOT operation acting on the input variables
Figure 2.42 Origin of the inverting
characteristic of CMOS gates
Introduction to VLSI Circuits and Systems, NCUT
Structured Logic Design
(2/4)
(a) Series-connected
nFETs
(b) Parallel-connected
nFETs
Figure 2.43 nFET logic
formation
Figure 2.44 nFET AOI circuit
Figure 2.45 nFET OAI circuit
Introduction to VLSI Circuits and Systems, NCUT
Structured Logic Design
(3/4)
(a) Parallel-connected
pFETs
(a) pFET AOI circuit
(b) pFET OAI circuit
(b) Series-connected
pFETs
Figure 2.46 pFET logic formation
Figure 2.47 pFET arrays for AOI and OAI
gates
Introduction to VLSI Circuits and Systems, NCUT
Structured Logic Design
(4/4)
(a) AOI circuit
(b) OAI circuit
Figure 2.48 Complete CMOS AOI and OAI
circuits
Introduction to VLSI Circuits and Systems, NCUT
Bubble Pushing
(a) NAND - OR
(a) Parallel-connected
pFETs
(b) NOR - AND
Figure 2.52 Bubble pushing using DeMorgan
rules
(b) Series-connected
pFETs
Figure 2.51 Assert-low models for
pFETs
Introduction to VLSI Circuits and Systems, NCUT
XOR and XNOR Gates
An important example of using
an AOI circuit is constructing
Exclusive-OR (XOR) and
Exclusive-NOR circuits
a b a b a b
(2.71)
a b a b a b
(2.72)
a b ( a b) a b a b
(2.73)
a b a b a b
(2.74)
(a) Exclusive-OR
Figure 2.57 AOI XOR and XNOR gates
(a) AOI22
Figure 2.56 XOR
(b) Exclusive-NOR
(b) AOI321
(c) AOI221
Figure 2.58 General naming
convention
Introduction to VLSI Circuits and Systems, NCUT
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
Introduction to VLSI Circuits and Systems, NCUT
Transmission Gate Circuits
A CMOS TG is created by connecting an nFET and pFET in parallel
Bi-directional
Transmit the entire voltage range [0, VDD]
y x s iff
s 1
(2.78)
Figure 2.60 Transmission gate (TG)
Introduction to VLSI Circuits and Systems, NCUT
Analysis of CMOS TG (1/4)
Four representations of CMOS Transmission Gate (TG)
A : Input
B : Output
C : Control Signal
0, Z (high impedance)
1, B A
Introduction to VLSI Circuits and Systems, NCUT
Analysis of CMOS TG (2/4)
Case (A) Vin=Vdd, C=Vdd (Both transistors ON)
NMOS :
PMOS :
Vds , n VDD Vout
Vgs , n VDD Vout
Vds , p Vout VDD
Vgs , p VDD
NMOS operation :
PMOS operation :
1. Trun off , Vout VDD Vt , n
2. Saturation, Vout VDD Vt , n
1. Saturation, Vout Vt , p
2. Linear , Vout Vt , p
PMOS is always ON regardless of Vout Value
Region I
Region II
nMOS: saturation
pMOS: saturation
0V
nMOS: saturation
pMOS: linear reg.
|Vt,p|
Region III
Total Current from I/P to O/P: ID = IDS,n+ISD,p
Equivalent resistance of NMOS and PMOS
nMOS: cut-off
pMOS: linear reg.
(VDD-Vt,n)
VDD
Vout
Summary of operating regions of MOS
out
reg , n VDDIdsV
, reg , p
,n
VDD Vout
Isd , p
Equivalent R of TG = reg,n // reg,p
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Analysis of CMOS TG (3/4)
Region (I): Vout < |Vt,p|
NMOS: saturation
{ PMOS: saturation
Region 1
2(VDD Vout )
n (VDD Vout Vt , n) 2
2(VDD Vout )
reg , p
p (VDD Vt , p ) 2
reg , n
Region (II): |Vt,p| < Vout < (VDD-Vt,n)
Region 2
nMOS: saturation
pMOS: saturation
0V
NMOS: saturation
PMOS: linear reg.
nMOS: saturation
pMOS: linear reg.
|Vt,p|
Region 3
nMOS: cut-off
pMOS: linear reg.
(VDD-Vt,n)
VDD
Vout
Note:
NMOS source-to-substrate voltage
2(VDD Vout )
= VSB,n = Vout - 0 = Vout
reg , n
2
n (VDD Vout Vt , n )
(Body Effect)
2(VDD Vout )
PMOS source-to-substrate voltage
reg , p
2
p [2(VDD Vt , p )(VDD Vout ) (VDD Vout ) ]
= VSB,p = 0 - 0 = 0 (constant)
(Vgs-Vt)
Vds
(Vds)2
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Analysis of CMOS TG (4/4)
Region (III): Vout > (VDD-|Vt,p|)
cut-off
{ NMOS:
PMOS: linear reg.
Region 1
nMOS: saturation
pMOS: saturation
reg , n , open
reg , p
Region 2
2
( simplify )
p [2(VDD Vt , p ) (VDD Vout )]
0V
nMOS: saturation
pMOS: linear reg.
|Vt,p|
Region 3
nMOS: cut-off
pMOS: linear reg.
(VDD-Vt,n)
VDD
Total resistance of CMOS TG v.s. Vout
Equivalent resistance of TG is relatively
constant
Individual reg. of NMOS and PMOS are
strongly dependent on Vout!!
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Vout
Logic Design using TG
(1/3)
Multiplexors
TG based 2-to-1 multiplexor
F P0 s P1 s
(2.79)
Figure 2.61 A TG-based 2-to-1
multiplexor
The 2-to-1 extended to a 4:1 network by using the 2-bit selector word (s 1, so)
F P0 s1 s0 P1 s1 s0 P2 s1 s0 P3 s1 s0
(2.80)
Introduction to VLSI Circuits and Systems, NCUT
Logic Design using TG
(2/3)
TG based XOR/XNOR
a b a b a b a b
a b a b a b
(2.81)
(2.82)
(b) XNOR
circuit
Figure 2.62 TG-based exclusive-OR and exclusive-NOR
circuits
(a) XOR circuit
TG based OR gate
f a (a ) a b
a a b
ab
Figure 2.63 A TG-based OR
(2.83)
Introduction to VLSI Circuits and Systems, NCUT
Logic Design using TG
(3/3)
Alternate XOR/XNOR Circuits
Mixing TGs and FETs which are designed for exclusive-OR and equivalence
(XNOR) functions
Its important in adders and error detection/correction algorithms
Figure 2.64 An XNOR gate that used both TGs and
FETs
Introduction to VLSI Circuits and Systems, NCUT
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
Introduction to VLSI Circuits and Systems, NCUT
Clock and Dataflow
Control
Synchronous digital design using a clock signal
Simply, the switching characteristics of TGs
1
T
(2.84)
(a) Closed switch
Figure 2.65 Complementary clocking signals
As Figure 2.66(b), when TG is off, the value of y = x for
a very short time thold. If we use a high-frequency clock
then the periodic open-closed change occurs at every
half clock cycle
(T / 2) t hold
(b) Open switch
Figure 2.66 Behavior of a clocked TG
Introduction to VLSI Circuits and Systems, NCUT
Clock and Dataflow Control Using
TGs
Data Synchronization using transmission
gates
To use clocked TGs for data flow control,
we place oppositely phased TGs at the
inputs and outputs of logic blocks
Figure 2.68 Block-level system timing
diagram
In this scheme, data moves through a
logic block every half cycle
Since the logic blocks are arbitrary, it
can be used as the basis for building
very complex logic chains
Synchronize the operations performed
on each bit of an n-bit binary word
Figure 2.67 Data synchronization using transmission
gates
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A Synchronized Word
Adder
In figure 2.69(a), the input word an-1a0 and
bn-1b0 are controlled by the clock plane,
while the sum sn-1s0 is transferred to the
output when 0
Every bit in a word is transmitted from one
point to another at the same time, which allows
us to track the data flow through the system
(a) Clocked adder
In figure 2.69(b), a larger scale with the ALU
(arithmetic and logic unit)
Input A and B are gated into the ALU by the
plane
control signal
The result word Out is transferred to the next
0
stage when 1 , i.e.,
(b) Clocked ALU
Figure 2.69 Control of binary
words using clocking planes
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Clock and Dataflow
Control
Clocked transmission gates synchronize the flow of signals, but the line
themselves cannot store the values for times longer than thold
(a) Logic diagram
(a) Logic diagram
(b) CMOS circuit
(b) CMOS circuit
Figure 2.70 SR latch
Figure 2.71 Clocked SR latch
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