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Folded Cascode Op-Amp Design & Specs

This document summarizes the design and simulation of a folded cascode op-amp. It includes the final schematic with component sizes, transient response simulations showing gain, phase margin, bandwidth, and output swing. Process variation and temperature simulations from 0 to 100 degrees Celsius are presented. Specification requirements for gain, phase margin, bandwidth, and output swing are listed along with the simulated results meeting requirements. The layout design and DRC/LVS checks are briefly mentioned at the end.

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Jan Philip Labayo
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183 views17 pages

Folded Cascode Op-Amp Design & Specs

This document summarizes the design and simulation of a folded cascode op-amp. It includes the final schematic with component sizes, transient response simulations showing gain, phase margin, bandwidth, and output swing. Process variation and temperature simulations from 0 to 100 degrees Celsius are presented. Specification requirements for gain, phase margin, bandwidth, and output swing are listed along with the simulated results meeting requirements. The layout design and DRC/LVS checks are briefly mentioned at the end.

Uploaded by

Jan Philip Labayo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

ECEE-403 ELECTIVE 3

MALIBIRAN, MARY JANE B.


ECE-4201
Phillip E. Allen and Douglas R. Holberg(2002), “CMOS Analog Circuit Design, 2nd Edition”

FOLDED CASCODE OP-AMP


FINAL SCHEMATIC DESIGN
COMPONENT SIZES

TRANSISTOR, RESISTOR AND SIZE SIZE


CAPACITOR (WIDTH) (LENGTH)

M1, M2 40u 2u
M3 12u 2u
M4,M5,M6,M7,M13,M14 16.6u 2u

M8.M9,M10,M11 7.6u 2u
M12 8u 2u
R1 10K
R2 30K
CL 1pF
FOLDED CASCODE OP-AMP
SIMULATIONS
TRANSIENT RESPONSE
OUTPUT SWING ≈ -930 mV – 910 mV
GAIN,PHASE MARGIN, GBW

GAIN = 64.309 dB
PHASE MARGIN = 63.999 degrees
GBW = 23.6466 MHz
PROCESS VARIATION
TEMPERATURE = 0 DEGREES

MODEL GAIN PHASE BANDWIDTH


MARGIN

tt 64.319 dB 63.987 degrees 26.4617MHz

ff 44.78 dB 59.290 degrees 24.4034 MHz

ss 59.317 dB 66.508 degrees 18.0526 MHz

fs 64.69 dB 63.34 degrees 25.2231 MHz

sf 64.459 dB 63.903 degrees 28. 5824 MHz

mc 64.461dB 63.987 degrees 26.4617 MHz


TEMPERATURE = 27 DEGREES

MODEL GAIN PHASE BANDWIDTH


MARGIN

tt 64.465 dB 64.928 degrees 22.5289MHz

ff 45.115 dB 58.519 degrees 22.637MHz

ss 59.375 dB 66.784 degrees 16.4161MHz

fs 59.15 dB 64.343 degrees 21.7186MHz

sf 64.285 dB 63.792 degrees 25.6089MHz

mc 64.309 dB 63.999 degrees 23.6466MHz


TEMPERATURE = 75 DEGREES

MODEL GAIN PHASE BANDWIDTH


MARGIN

tt 59.723 dB 64 degrees 20.5376 MHz

ff 45.4 dB 57.983 degrees 20.8803 MHz

ss 59.201 dB 67.307 degrees 14.4543 MHz

fs 59.772 dB 64.531 degrees 18.9168 MHz

sf 59.238 dB 63.39 degrees 21.9047 MHz

mc 59.636 dB 64 degrees 20.5376 MHz


TEMPERATURE = 100 DEGREES

MODEL GAIN PHASE BANDWIDTH


MARGIN

tt 59.856 dB 64.123 degrees 19.3142 MHz

ff 45.15 dB 57.94 degrees 20.0538 MHz

ss 59.873 dB 66.798 degrees 14.2987 MHz

fs 59.685 dB 64.771 degrees 17.7267 MHz

sf 59.776 dB 63.713 degrees 20.653 MHz

mc 60.053 dB 64.123 degrees 19.3142 MHz


SPECIFICATIONS: REQUIRED: SIMULATED:

GAIN >60 dB 64.309 dB

PHASE MARGIN At least 60 degrees 63.999 degrees

GAIN BANDWIDTH ≥ 10 MHz 23.6466 MHz

OUTPUT SWING 300 mV -930 mV – 910 mV

Low to High = 6.8 V/usec


SLEW RATE N/A High to Low = 7.9 V/usec

ICMR N/A -560 mV – 580 mV

CL 10 pF 10 pF
LAYOUT DESIGN
DRC CHECK (Design Rule Check)
LVS Test (Layout Vs Schematic)

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