ARM - Advanced RISC Machines
RISC- Reduce Instruction Set Computers
ARM Design Philosophy
• ARM Core uses a RISC architecture
• ARM licenses its cores out and other
companies make processors based on its
cores and
• ARM processor core based
microcontrollers
• Von Neumann architecture.
ARM Design Philosophy
• Reduce power consumption
• High code density
• Price sensitive
• Reduce the area of the die taken up by the
embedded processor
• Incorporated hardware debug technology
(ICE-In circuit emulator)
ARM processor core based
microcontrollers
• Key component of many 32 –bit embedded
systems and Portable Consumer devices
• ARM1 prototype in 1985
• One of the ARM’s most successful cores is the
ARM7TDMI,provides high code density and
low power consumption.
ARM7TDMI
• T –Thumb 16 bit compressed instruction set
• D – on chip Debug request
• M – enhanced Multiplier(yields 64 bit result)
• I – Embedded ICE hardware to give on-chip
breakpoint and watchpoint support
ICE – in circuit emulator for debugging
The RISC Design Philosophy
• RISC is characterized by limited number of
instructions
• A complex instruction is obtained as a sequence
of simple instructions.
• So, in RISC processor, software is complex but the
processor architecture is simple.
• Large number of registers are required.
• Pipelined instruction execution.
• Ex : ARM, ATMEL AVR, MIPS, Power PC etc
The CISC Design Philosophy
• CISC is characterized by large instruction set.
• The aim of designing CISC processors is to
reduce software complexity by increasing the
complexity of processor architecture.
• Very small number of registers are available.
• Ex : Intel X86 family, Motorola 68000 series.
RISC –4 major design rules
1. Instructions
• Reduced Number of Instructions
• Execute in a single cycle
• The compiler synthesizes complicated
operations
• Each instruction is a fixed length
2. Pipelines
• The processing of instructions is broken down
into smaller units that can be executed in
parallel by pipelines
• Pipeline advances by one step on each cycle
for maximum throughput
3. Registers
• Have a large general purpose register set
• Any register can contain either data or address
• CISC has dedicated registers for specific
purposes.
4. Load –Store Architecture
• Separate load and store instructions transfers
data between the register bank and external
memory
ARM Architecture
Based on RISC architecture with
enhancements to meet requirements of
embedded applications
o A large uniform register file
o Load/store architecture
o Uniform and fixed length instructions
o 32 bit processor
o Good speed/power consumption ratio
o High code density
Load-store architecture
Instruction set will only process (add, subtract and so
on) values which are in registers and place the results
into a register
The operations which apply to memory state are
• the ones which copy memory values into
registers(load instructions)
• or copy register values into memory (store
instructions)
Load-Store Architecture
cont…
ARM instructions fall into one of the following
categories
1. Data processing instructions(use and change
only register values)
2. Data transfer instructions(load and store
instructions)
3. Control flow instructions[branch instructions,
branch and link instructions(similar to interrupt)
or supervisor calls
Instruction set for Embedded Systems
• Variable cycle execution for certain
instructions
• Inline barrel shifter leading to more complex
instructions
• Thumb 16 –bit instructions
• Conditional execution
• Enhanced Instructions
Enhancements to Basic RISC Features
Control over ALU and shifter for every data
processing operations to maximize their usage
Auto-increment and auto-decrement addressing
modes to optimize program loops
Multiple Load/Store data elements to maximize
throughput
Conditional execution of instruction to maximize
throughput
Overview: Core Data Path
Data items are placed in register file
• No data processing instructions directly manipulate data in
memory
Instructions typically use two source registers and
single result or destination register
A Barrel shifter on the data path can pre-process
data before it enters ALU
Increment/Decrement logic can update register
content for sequential access independent of ALU
Multiply and Accumulate
Registers
General purpose registers hold either data or address
All registers are of 32 bits
In user mode 16 data registers and 2 status registers
are visible
Data registers: r0 to r15
• Three registers r13, r14 and r15 perform special functions
• r13: stack pointer
• r14: link register (where return address is stored whenever
a subroutine is called)
• r15: program counter
