UNIT-1 : LECTURE -4
Bus and Memory Transfer
Mr. Mukul Varshney
contents
• Register Transfer Language
• Register Transfer
• Bus and Memory Transfers
Mr. Mukul Varshney
4-1 Register Transfer Language (RTL)
Digital System: An interconnection of
hardware modules that do a certain task on the
information.
Registers + Operations performed on the data
stored in them = Digital Module
Modules are interconnected with common data
and control paths to form a digital computer
system
Mr. Mukul Varshney
4-1 Register Transfer Language cont.
Microoperations: is an elementry operations
executed on data stored in one or more registers.
For any function of the computer, a sequence of
microoperations is used to describe it
The result of the operation may be:
replace the previous binary information of a
register or
transferred to another register
Shift Right Operation
101101110011 010110111001
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ADD R1,R2
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4-1 Register Transfer Language cont.
The internal hardware organization of a
digital computer is defined by specifying:
The set of registers it contains and their function
The sequence of microoperations performed on the
binary information stored in the registers
The control that initiates the sequence of
microoperations
Registers + Microoperations Hardware +
Control Functions = Digital Computer
Mr. Mukul Varshney
4-1 Register Transfer Language cont.
Register Transfer Language (RTL) : a symbolic
notation to describe the microoperation
transfers among registers
Next steps:
Define symbols for various types of
microoperations,
Describe the hardware that implements these
microoperations
Mr. Mukul Varshney
4-2 Register Transfer (our first
microoperation)
Computer registers are designated by capital
letters (sometimes followed by numerals) to
denote the function of the register
R1: processor register
MAR: Memory Address Register (holds an address for
a memory unit)
PC: Program Counter
IR: Instruction Register
SR: Status Register
Mr. Mukul Varshney
4-2 Register Transfer cont.
The most common way to represent a
register ,is by rectangle box with name of
register inside
The individual flip-flops in an n-bit register are
numbered in sequence from 0 to n-1 (from the
right position toward the left position)
7 6 5 4 3 2 1 0
R1 R1
Register R1 Showing individual bits
A block diagram of a register
Mr. Mukul Varshney
4-2 Register Transfer cont.
Other ways of drawing the block diagram of a register:
15 0
PC
Numbering of
bits
A 16 bit register is partitioned into two parts, bit 0 through 7 are
assigned the symbol L(for low byte) and 8-15 are assigned the
symbol H( for high byte)
15 87 0
Upper byte PC(H) PC(L) Lower byte
Partitioned into two
parts
Mr. Mukul Varshney
4-2 Register Transfer cont.
Information transfer from one register to another is
described by a replacement operator: R2 ← R1
This statement denotes a transfer of the content of
register R1 into register R2
The transfer happens in one clock cycle
The content of the R1 (source) does not change
The content of the R2 (destination) will be lost and
replaced by the new data transferred from R1
We are assuming that the circuits are available from the
outputs of the source register to the inputs of the
destination register, and that the destination register
has a parallel load capability
Mr. Mukul Varshney
4-2 Register Transfer cont.
Conditional transfer occurs only under a
control condition
Representation of a (conditional) transfer
P: R2 ← R1
A binary condition (P equals to 0 or 1)
determines when the transfer occurs
The content of R1 is transferred into R2 only if
P is 1
Mr. Mukul Varshney
4-2 Register Transfer cont.
Hardware implementation of a controlled transfer: P: R2 ← R1
Block diagram: Control P Load
R2 Clock
Circuit
R1
Timing diagram t t+1
Clock
Synchronized
Load
with the clock
Transfer occurs here
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4-2 Register Transfer cont.
Unconditional
R1 ← R2
Conditional
P: R1 ← R2
Simultaneous
R1 ← R2 , R3 ← R2
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SIMULTANEOUS OPERATIONS
If two or more operations are to occur
simultaneously, they are separated with commas
P: R3 R5 ,, MAR IR
Here, if the control function P = 1, load the contents
of R5 into R3, and at the same time (clock), load the
contents of register IR into register MAR
4-2 Register Transfer cont.
Basic Symbols for Register Transfers
Symbol Description Examples
Letters & Denotes a register MAR, R2
numerals
Parenthesis Denotes a part of a R2(0-7), R2(L)
( ) register
Arrow ← Denotes transfer of R2 ← R1
information
Comma , Separates two R2 ← R1, R1 ←
microoperations R2
Mr. Mukul Varshney
4-2 Register Transfer cont.
Q1.Show the H/W implementation to the given
statement
T1 = B A
T2 = B C
Q1.Show the H/W implementation to the given
statement
xy : A B , B A
Mr. Mukul Varshney
4-2 Register Transfer cont.
Every statement written in a register transfer notation implies a H/W
construction for implementing the transfer.
The internal H/W organization of a digital computer is best defined
by specifying :
1. The set of register it contains.
2. Sequence of micro-operation performed on the binary information
stored in the register.
3. The control that initiates the sequence of micro-operation.
Mr. Mukul Varshney
4-3 Bus and Memory Transfers
A shared communication path consisting of
one or more connection lines is known as bus
Bus transfer : The transfer of data through bus
is known as bus transfer.
Memory Transfer : When a data is read from
memory or is stored in memory is referred to
as memory transfer.
Mr. Mukul Varshney
4-3 Bus and Memory Transfers
Paths must be provided to transfer information
from one register to another
A Common Bus System is a scheme for
transferring information between registers in a
multiple-register configuration
A bus: set of common lines, one for each bit of a
register, through which binary information is
transferred one at a time
Control signals determine which register is
selected by the bus during each particular
register transfer
Mr. Mukul Varshney
4-3 Bus and Memory Transfers
Register A Register B Register C Register D
Bus lines
Register D Register C Register B Register A
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
D3 D2 D1 D0 C3 C2 C1 C0 B3 B2 B1 B0 A3 A2 A1 A0
D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0
3 2 1 0 3 2 1 0 3 2 1 0
3 2 1 0 S0
S0 S0 S0
MUX3 MUX2 MUX1 MUX0 S1
S1 S1 S1
4-Line Common Bus
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4-3 Bus and Memory Transfers
A bus system with multiplexer:
For k register of n bits, each produce an n– line
common bus.
The number of multiplexer needed is equal to
n( no of bits in each register)
The size of each multiplexer must be k ×1
Mr. Mukul Varshney
4-3 Bus and Memory Transfers
The transfer of information from a bus into one of
many destination registers is done:
By connecting the bus lines to the inputs of all
destination registers and then:
activating the load control of the particular destination
register selected
We write: R2 ← C to symbolize that the content
of register C is loaded into the register R2 using
the common system bus
It is equivalent to: BUS ←C, (select C)
R2 ←BUS (Load R2)
Mr. Mukul Varshney
4-3 Bus and Memory Transfers: Three-
State Bus Buffers
A bus system can be constructed with three-
state buffer gates instead of multiplexers
A three-state buffer is a digital circuit that
exhibits three states: logic-0, logic-1, and high-
impedance (Hi-Z)
Control input C
Normal input A Output B
Three-State Buffer
Mr. Mukul Varshney
4-3 Bus and Memory Transfers: Three-
State Bus Buffers cont.
C=1
Buffer
A B A B
C=0
Open Circuit
A B A B
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TRANSFER FROM BUS TO A DESTINATION
Bus lines
REGISTER
Load
Reg. R0 Reg. R1 Reg. R2 Reg. R3
D 0 D1 D2 D 3
z E (enable)
Select 2x4
w
Decoder
Three-State Bus Buffers
Normal input A Output Y=A if C=1
High-impedence if C=0
Control input C
Bus line with three-state buffers
Bus line for bit 0
A0
B0
C0
D0
S0 0
Select 1
S1 2
Enable 3
4-3 Bus and Memory Transfers: Three-
State Bus Buffers cont.
S1 0
Select
S0 1
Bus line for bit 0
2×4 A0
Decoder 2
Enable E
3
B0
C0
Bus line with three-state buffer
(replaces MUX0 in the previous D0
diagram)
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A0 A1
2X4 B0 B1
DECODER
C0 C1
D0 D1
Output for 0 bit Output for bit 1
Mr. Mukul Varshney
4-3 Bus and Memory Transfers:
Memory Transfer
Memory read : Transfer from memory
Memory write : Transfer to memory
Data being read or wrote is called a memory
word (called M)- (refer to section 2-7)
It is necessary to specify the address of M when
writing /reading memory
This is done by enclosing the address in square
brackets following the letter M
Example: M[0016] : the memory contents at
address 0x0016
Mr. Mukul Varshney
4-3 Bus and Memory Transfers: Memory
Transfer cont.
Assume that the address of a memory unit is
stored in a register called the Address Register
AR
Lets represent a Data Register with DR, then:
Read: DR ← M[AR]
Write: M[AR] ← DR
Mr. Mukul Varshney
4-3 Bus and Memory Transfers: Memory
Transfer cont.
AR
x0C 19
x12 x0E 34
R1 x10 45
100 x12 66
x14 0
x16 13
R1←M[AR] x18 22
RAM
R1 R1
100 66
Mr. Mukul Varshney
