Computer Arithmetic 1

COMPUTER ARITHMETIC

• Arithmetic with Signed-2's Complement Numbers

• Multiplication and Division

• Floating-Point Arithmetic Operations

• Decimal Arithmetic Unit

• Decimal Arithmetic Operations

Computer Arithmetic 2

Computer Arithmetic

• The Four basic arithmetic operations

– Addition, Subtraction, Multiplication and division
• Arithmetic processor is part of a processor unit that
executes arithmetic operations.
• The data resides in processor registers during
execution of an arithmetic instruction.
• Data may be in fixed or floating point form.
• Negative numbers may be in the form of signed
magnitude or signed complement representation.
Computer Arithmetic 3

FIXED POINT NUMBERS

Numbers: Fixed Point Numbers and Floating Point Numbers

Binary Fixed-Point Representation

X = xnxn-1xn-2 ... x1x0

Sign Bit(xn): 0 for positive and 1 for negative

Remaining Bits(xn-1xn-2 ... x1x0)

Computer Arithmetic 4

SIGNED NUMBERS
Need to be able to represent both positive and negative numbers

- Following 3 representations

Signed magnitude representation

Signed 1's complement representation
Signed 2's complement representation

Example: Represent +9 and -9 in 7 bit-binary number

Only one way to represent +9 ==> 0 001001

Three different ways to represent -9:
In signed-magnitude: 1 001001
In signed-1's complement: 1 110110
In signed-2's complement: 1 110111
Computer Arithmetic 5 Addition and Subtraction

SIGNED MAGNITUDE ADDITION AND SUBTRACTION

Addition: A+B; A: Augend; B: Addend
Subtraction: A - B: A: Minuend; B: Subtrahend
Add Subtract Magnitude
Operation Magnitude When A > B When A < B When A = B
(+A) + (+B) +(A + B)
(+A) + (- B) +(A - B) - (B - A) +(A - B)
(- A) + (+B) - (A - B) +(B - A) +(A - B)
(- A) + (- B) - (A + B)
(+A) - (+B) +(A - B) - (B - A) +(A - B)
(+A) - (- B) +(A + B)
(- A) - (+B) - (A + B)
(- A) - (- B) - (A - B) +(B - A) +(A - B)
Computer Arithmetic XOR6 Truth Table Addition and Subtraction

SIGNED MAGNITUDE ADDITION AND SUBTRACTION

Hardware Implementation
Bs B Register

AVF Complementer M(Mode Control)

E Output Input
Parallel Adder
Carry Carry
S
As A Register Load Sum

• Complementer consists of XOR gates

• When M=0, B is transferred to adder and input carry is 0, The
output S of adder is A+B
XOR Truth table
• When M=1, 1’s complement of B is applied to adder and input
Input
carry is 1, The output S of adder is A+B’+1 or A-B.
Output
• The output carry is transferred to flip flop E A B
• Add over flow AVF flip flop holds overflow bit when A+B 0 0 0
0 1 1
1 0 1
1 1 0
Computer Arithmetic 7

Flowchart for Addition and Subtraction

Computer Arithmetic 8

Two’s Complement Subtraction

EXAMPLE
Subtract 18 - 7 using 8-bit two’s complement arithmetic.
18 - 7 is the same as 18 + (-7), so add 18 plus negative 7.
SOLUTION:

Convert -7 to two’s complement

+18 = 0001 0010
True Binary = 0000 0111
-7 = 1111 1001
One’s complement = 1111 1000
Sum = 0000 1011 = 11
Add 1 +1
Two’s complement = 1111 1001

Note: The carry out of MSB is

ignored. It will always occur for
positive sums.
Computer Arithmetic 9 Addition and Subtraction

SIGNED 2’S COMPLEMENT ADDITION AND SUBTRACTION

Computer Arithmetic 10 Addition and Subtraction

SIGNED 2’S COMPLEMENT ADDITION AND SUBTRACTION

Hardware
B Register

V Complementer and
Parallel Adder
Overflow

AC

Algorithm
Subtract Add

Minuend in AC Augend in AC
Subtrahend in B Addend in B

AC  AC + B’+ 1 AC  AC + B
V  overflow V  overflow

END END
Computer Arithmetic 11

MULTIPLICATION
Computer Arithmetic 13

Hardware for Multiply operation

Computer Arithmetic 14 Multiplication

EXAMPLE

Multiplicand B=10111 E A Q SC
Multiplier in Q 0 00000 10011 101
Q0 = 1; add B 10111
First partial product 0 10111
Shift right EAQ 0 01011 11001 100
Q0 = 1; add B 10111
Second Partial Product 1 00010
Shift right EAQ 0 10001 01100 011
Q0 = 0; shift right EAQ 0 01000 10110 010
Q0 = 0; shift right EAQ 0 00100 01011 001
10111
Q0 = 1; add B
0 11011
Fifth partial product
0 01101 10101 000
Shift right EAQ
Final Product in AQ = 0110110101
Computer Arithmetic 15 Multiplication

SIGNED MAGNITUDE MULTIPLICATION

Bs
Hardware
B Register Sequence Counter

Complementer and
Parallel Adder

As Qs Qn

0 E AC Q Register
EAQ

B <- Multiplicand B
Q <- MultiplierA
Algorithm
As,Qs <- Qs  Bs
A <- 0, E <- 0
SC <- n-1

=0 =1
Q0

EA <- A + B

shr EAQ
=0 SC <- SC+1
END =0
Product SC
in AQ
Computer Arithmetic 16 Multiplication
BOOTH MULTIPLICATION ALGORITHM FOR SIGNED 2’S
COMPLEMENT
Multiplier
Strings of 0’s: No addition; Simply shifts
Strings of 1’s: String of 1’s from mp to mq: 2p+1 - 2q

Example
001110 (14) -> p = 3, q = 1
001110 = 23+1 - 21

M * 14 = M24 - M21

Algorithm
[1] Subtract multiplicand for the first least significant 1
in a string of 1’s in the multiplier
[2] Add multiplicand for the first 0 after the string
of 1’s in the multiplier
[3] Partial Product does not change when the
multiplier bit is identical to the previous bit

110010 = -24 + 22 - 21 = -16 + 4 - 2 = -14

subtract Add subtract

24 22 21
Computer Arithmetic 17

Hardware for Booth Algorithm

Computer Arithmetic 18 Multiplication

BOOTH ALGORITHM FOR SIGNED 2’S COMPLEMENT

B <- Multiplicand B
Q <- Multiplier A

AC <- 0
Qn+1 <- 0
SC <- n

10 QnQn+1 01
Qn+1 : shifted out bit
? on shr of Q
11
00
AC<-AC+B’+1 AC <- AC + B

ashr(AC&Q)
SC <- SC - 1

0 SC
?
=0

END
Computer Arithmetic 19 Multiplication

EXAMPLE OF BOOTH MULTIPLIER

N=5, B=-9, A=-13

B = 10111
QnQn+1 B’+1=01001 AC Q Q n+1 SC
Initial 00000 10011 0 101
10 Subtract B 01001
01001
ashr 00100 11001 1 100
11 ashr 00010 01100 1 011
01 Add B 10111
11001
ashr 11100 10110 0 010
00 ashr 11110 01011 0 001
10 Subtract B 01001
00111
ashr 00011 10101 1 000
Computer Arithmetic 20 Multiplication

ARRAY MULTIPLIER
A = a1a0: Multiplier
B = b1b0: Multiplicand b1 b0
a1 a0
C = B * A = c3c2c1c0 a0b1 a0b0
a1b1 a1b0
c3 c2 c1 c0

b1 b0
a0

b1 b0
a1

HA HA
C S C S

c3 c2 c 1 c0
Computer Arithmetic 21 Multiplication

ARRAY MULTIPLIER (4-BIT X 3-BIT)

a0
b3 b2 b1 b0
a1
b3 b2 b1 b0
0

Addend Augend
4-bit Adder
Sum and Carry Outputs
a2
b3 b2 b1 b0

Addend Augend
4-bit Adder
Sum and Carry Outputs

c6 c5 c4 c3 c2 c1 c0
Computer Arithmetic 22

• For j multiplier bits and k multiplicand bits we need j

* k AND gates and (j-1) K bits adders to produce j+k
bits
Computer Arithmetic 23

Division
Computer Arithmetic 24

Example of Devision
Computer Arithmetic 25

Division

• Hardware for division is same as multiplication

• Register EAQ is shifted to the left with 0 inserted into

Qn and previous value of E lost

Computer Arithmetic 26

Divide Overflow
Computer Arithmetic 27 Division

FLOWCHART OF DIVIDE OPERATION

Dividend in AQ
Divisor in B

Qs As  Bs shl EAQ

SC<- n - 1
0 1
E
EA  A + B’+1
EA  A+B’+1 A  A+B’+1
1 0
E
1
A B A<B E
0(A<B) A B
EA  A+B EA  A+B EA  A+B Q0  1
DVF  1 DVF  0

SC  SC-1

0 0
END SC
(Divide overflow)
END
(Quotient in Q
Remainder in R)
Computer Arithmetic 28

LOGIC FOR DIVIDE OPERATION

Computer Arithmetic 29 Division

DIVISION
A/B=Q+R
A: Dividend; B: Divisor; Q: Quotient; R: Remainder
Divisor B = 10001, B’+ 1 = 01111
E A Q SC
Dividend: 01110 00000 5
shl EAQ 0 11100 00000
add B’+1 01111
E=1 1 01011
Set Q0=1 1 01011 00001 4
shl EAQ 0 10110 00010
Add B’+1 01111
E=1 1 00101
Set Q0=1 1 00101 00011 3
shl EAQ 0 01010 00110
add B’+1 01111
E=0; Q0=0 0 11001 00110
add B 10001
restore remainder 1 01010 2
shl EAQ 0 10100 01100
add B’+1 01111
E=1 1 00011
1 00011 01101 1
Set Q0=1 0 00110 11010
shl EAQ 01111
add B’+1 0 10101 11010
E=0; Q0=0 10001
add B 1 00110 11010 0
restore remainder
neglect E 00110
remainder in A 11010
quotient in Q
Computer Arithmetic 30 Floating Point Arithmetic

FLOATING POINT ARITHMETIC OPERATIONS

F = m x re
where m: Mantissa
r: Radix
e: Exponent

Registers for Floating Point Arithmetic

Bs B b BR

Parallel Adder
E Parallel Adder and Comparator

As A1 A a AC

Qs Q q QR
Computer Arithmetic 31

Add/Substract
Computer Arithmetic 32 Floating Point Arithmetic

FLOATING POINT ADD AND AUBTRACT

=0 BR  0 AC
0
C
H =0 a<b a>b
E a:b
C AC  BR Align
K shr A shr B Mantissa
add op a  a+1 b  b+1
F sub
sub op add
O As  A’s
R

0 1 1
As  Bs As  Bs
+ or - of
0 0 mantissa

EA<-A+B’+1 EA  A+B

A  A’+1 0 E
As  A’s 1
0 =0
A
0 Normalization
A1 AC  0 E
shl A 1 shr A
a  a+1 A1  E
a  a+1
END
Computer Arithmetic 33

Multiplication
Computer Arithmetic 34 Floating Point Arithmetic

FLOATING POINT MULTIPLICATION

BR  Multiplicand
QR  Multiplier

=0
BR
0
=0
QR
0
AC  0
aq
aa+b
a  a - bias

Multiply mantissa
(finxed point
multiplication)

shl AQ 0 A1
aa-1
1

END
(Product is in AC)
Computer Arithmetic 35 Floating Point Arithmetic

FLOATING POINT DIVISION

BR  Divisor
AC  Dividend
=0
BR
0
=0 AC
0
QR  0 Qs  As + Bs
Q0
divide SC  n-1
by 0
EA  A+B’+1
1 E 0
A>=B A<B

A  A+B A  A+B
shr A
a  a+1

a  a+b’+1
a  a+bias
qa

Divide Magnitude of mantissa

as in fixed point numbers
Computer Arithmetic 36 BCD Arithmetic

BCD ADD

BCD digit < 10

BCD digit + BCD digit + carry =< 19

Binary Sum BCD Sum

K Z8 Z4 Z2 Z1 C S8 S4 S2 S1 Decimal
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 2
0 0 0 1 1 0 0 0 1 1 3
0 0 1 0 0 0 0 1 0 0 4
0 0 1 0 1 0 0 1 0 1 5
0 0 1 1 0 0 0 1 1 0 6
0 0 1 1 1 0 0 1 1 1 7
0 1 0 0 0 0 1 0 0 0 8
0 1 0 0 1 0 1 0 0 1 9
0 1 0 1 0 1 0 0 0 0 10
0 1 0 1 1 1 0 0 0 1 11
0 1 1 0 0 1 0 0 1 0 12
0 1 1 0 1 1 0 0 1 1 13
0 1 1 1 0 1 0 1 0 0 14
0 1 1 1 1 1 0 1 0 1 15
1 0 0 0 0 1 0 1 1 0 16
1 0 0 0 1 1 0 1 1 1 17
1 0 0 1 0 1 1 0 0 0 18
1 0 0 1 1 1 1 0 0 1 19
Computer Arithmetic 37 BCD Arithmetic

BCD ADDER
If we can convert Binary Sums to BCD Sum ,
we can use a binary adder to add two BCD numbers

SUM =< 9 19 >= SUM > 9

BCD Sum = Binary Sum BCD Sum = Binary Sum + 0110
BCD Carry = Binary Carry BCD Carry = Carry(Binary Sum + 0110)

4-bit Binary Add

1 0
K Take next
higher digit
Z8 0

1
1
Z4 done
0 ?
1 0 END
Z2

BCD Sum  Sum + 0110 BCD Sum = Sum

BCD C  Carry(BCD Sum) BCD C  Carry(Sum)
Computer Arithmetic 38 BCD Arithmetic

BCD ADDER HARDWARE

Addend Augend

Carry Out 4-bit Binary Addr

K Carry In
Z8 Z4 Z2 Z1

BCD Carry

0
0110
4-bit Binary Adder

S8 S 4 S 2 S 1
Computer Arithmetic 39 Decimal Arithmetic

DECIMAL ARITHMETIC OPERATIONS

Addition

- Identical to the BCD addition

- 9’s complement and 10’s complement are
identical to 1’s complement and 10’s
complement, respectively