Addressing Modes
SHUBHARAJ THAPA
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Table of Introduction Types of Conclusion
Addressing
contents modes with
examples
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Introduction
Addressing modes refer to the different methods used by the central processing unit
(CPU) to access data in memory or operands during instruction execution
An addressing mode specifies how the CPU calculates the effective memory address for
data or instructions based on the operands specified in the instruction
It is used to give programming flexibility to the user as well as to use the bit in the
address field of the instruction efficiently
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Types of addressing
modes
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Implied/Implicit Addressing modes
typically used for instructions that perform operations on fixed hardware registers or
have well-defined effects on specific memory locations
operands or addresses for instructions are not explicitly specified in the instruction itself
For example ADD X, PUSH Y, CLA,CME and so on
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Stack Addressing Mode
specific addressing mode utilized for accessing data or operands stored in the stack
memory
CPU implicitly uses the stack pointer (SP) register to keep track of the top of the stack
Typically involves following instruction
Push
Pop
Call
Return
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Immediate addressing mode
The operand value is directly specified in the instruction itself
It is useful for constants and small values that does not require memory access
Sometimes require more bits than the address
Fast to acquire and operand
For example ADD R1, #5
{ the opcode of instruction specifying addition operation , R1 is the register where the result
of addition will be stored and 5 is the immediate value which is the operand to be added to
the value in register R1 }
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Direct Addressing Mode
the operand's memory address is explicitly provided in the instruction
Faster than the other memory addressing modes
CPU directly accesses the memory location specified in the instruction to read or write
data
Too many bits are required to specify the address for a large physical memory space
For example LOAD R1, [0x1000]
Load: The opcode of the instruction, specifying the load operation
R1: The destination register where the data from memory will be loaded
[0x1000]: The memory address from which the data will be fetched
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Indirect Addressing Mode
the instruction specifies a memory address that contains the actual address of the data
Instead of directly providing the operand value or memory address in the instruction, the
CPU uses the provided memory address as a pointer to the location where the actual data
or operand is stored
For example Load R1, [R2]
Load:The opcode of the instruction, specifying the load operation
R1: The destination register where the data from memory will be loaded
[R2]: The memory address contained in register R2. This address points to the location in
memory where the actual data to be loaded is stored
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Register Direct Addressing Mode
the instruction directly specifies a register as the operand or data location
CPU uses the register identifier present in the instruction to access the data stored in that
register
the instruction explicitly names the register that contains the data to be processed,
eliminating the need to provide a memory address or calculate the address of the data
For example: ADD R1, R2
ADD: The opcode of the instruction, specifying the addition operation.
R1: The destination register where the result of the addition will be stored
R2: The source register from which the value will be added to the value in register R1
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Register Indirect Addressing Modes
instruction uses a register as a pointer to access data stored in memory
Instead of directly specifying the memory address in the instruction, the CPU uses the
content of the specified register as the memory address to fetch or store data
It allows for more flexible memory access and is often used for working with data
structures, arrays, or dynamically allocated memory
For Example LOAD R1, [R2]
Load:The opcode of the instruction, specifying the load operation
R1: The destination register where the data from memory will be loaded
[R2]: The memory address pointed to by register R2. The value in register R2 serves as a
pointer to the location in memory where the actual data to be loaded is stored
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Relative Addressing Mode
the memory address or operand is specified as an offset relative to the current location or
Program Counter (PC)
CPU uses the offset to calculate the actual memory address of the data or instruction to
be accessed
often used for implementing branching or jumping instructions, allowing the CPU to
perform conditional or unconditional jumps to different parts of the program
For example JUMP #10
JUMP: The opcode of the instruction, specifying the jump operation
#10: The relative offset of 10. This means the CPU will jump to the memory location that is
10 bytes ahead of the current instruction's address
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Indexed Addressing Mode
the instruction uses an index or an offset added to a base memory address to access data
in memory
CPU uses the contents of an index register, along with a base address specified in the
instruction, to calculate the effective memory address where the data or operand is
located
For Example: LOAD R1, [R2+ #4]
LOAD: The opcode of the instruction, specifying the load operation.
R1: The destination register where the data from memory will be loaded.
[R2 + #4]: The indexed addressing part. The CPU takes the value in register R2 (base
address) and adds an offset of 4 to it. The result is the effective memory address from which
the data will be fetched.
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Base Register Addressing Mode
It is a variation of indexed addressing mode but typically involves only one register,
known as the base register, instead of an explicit index register.
CPU uses the content of the base register as a starting address, and an offset (also called
displacement) is added to the base address to calculate the effective memory address
where the data or operand is located
For example LOAD R1, [R2+ #4]
LOAD: The opcode of the instruction, specifying the load operation.
R1: The destination register where the data from memory will be loaded.
[R2 + #4]: The base register addressing part. The CPU takes the value in register R2 (base
register) and adds an offset of 4 to it. The result is the effective memory address from which
the data will be fetched
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Auto-increment Addressing mode
automatically increments the value of a specific register after accessing the data at the
memory location it points to.
particularly useful when accessing elements in arrays or sequential data structures where
consecutive memory locations hold related data
For Example LOAD R1, [R2]+
LOAD: The opcode of the instruction, specifying the load operation.
R1: The destination register where the data from memory will be loaded.
[R2]+: The auto-increment addressing part. The CPU takes the value in register R2 (base
address) to access the data at that memory location. Afterward, it increments the value in R2
to point to the next element in the array or data structure
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Auto Decrement addressing mode
automatically decrements the value of a specific register after accessing the data at the
memory location it points to.
particularly useful when working with arrays or sequential data structures
For example LOAD R1, [R2]-
LOAD: The opcode of the instruction, specifying the load operation.
R1: The destination register where the data from memory will be loaded.
[R2]-: The auto-decrement addressing part. The CPU takes the value in register R2 (base
address) to access the data at that memory location. Afterward, it decrements the value in R2
to point to the previous element in the array or data structure
