COMPUTER ORGANIZATION

Unit-II PPT Slides

Text Books: (1) Computer Systems Architecture by M. Morris Mano
(2) Computer Organization by Carl Hamacher
 INDEX
UNIT-II PPT SLIDES
Sl. No. Module as per Session planner Lecture No
1. Register Transfer language L1
2. Register Transfer Bus and memory transfers L2
3. Arithmetic Micro-operations L3
4. Logic micro operations L4
5. Shift micro operations L5
6. Arithmetic logic shift unit L6
7. Instruction codes L7
8. Computer registers L8
9. Computer instructions L9
10. Instruction cycle L10
11. Memory-Reference Instructions L11
12. Input-output and Interrupt L12
13. STACK organization L13
14. Instruction formats L14
15. Addressing modes L15
16. DATA Transfer and manipulation L16
17. Program control L17
18. Reduced Instruction Set Computer L18
 REGISTER TRANSFER LANGUAGE
• Combinational and sequential circuits can be used to
create simple digital systems.
• These are the low-level building blocks of a digital
computer.
• Simple digital systems are frequently characterized in
terms of
– the registers they contain, and
– the operations that they perform.
• Typically,
– What operations are performed on the data in the
registers
– What information is passed between registers
 MICROOPERATIONS
• The operations executed on data stored in registers are
called microoperations.
• Examples of microoperations
– Shift
– Load
– Clear
– Increment
– Count
An elementary operation performed (during one clock pulse), on
the information stored in one or more registers.

R  f(R, R)
f: shift, load, clear,
increment, add,
subtract, complement,
Registe ALU 1 clock cycle
rs (f)
(R)
and, or, xor, …
 INTERNAL HARDWAREORGANIZATION OF A DIGITAL SYSTEM
• Definition of the internal hardware organization of a computer
- Set of registers it contains and their function
- The sequence of microoperations performed on the binary
information stored in the registers
- Control signals that initiate the sequence of
microoperations (to perform the functions)

REGISTER TRANSFER LANGUAGE

The symbolic notation used to describe the microoperation

transfers
among registers is called a Register transfer
language. Register transfer language
•A symbolic language
•A convenient tool for describing the internal
organization of
digital computers
 Register Transfer
• Registers are designated by capital letters, sometimes
followed by numbers (e.g., A, R13, IR).
• Often the names indicate function:
– MAR - memory address register
– PC - program counter
– IR - instruction register
• Information transfer from one register to another is
designated in symbolic form by means of a replacement
operator.

R2  R1

– In this case the contents of register R2 are copied (loaded)

into register R1 and contents of R1 remains same.
 Block diagram of a register

R1 7 6 5 4 3 2 1
0
Register R
Showing individual bits

15 8 7 0
15 0
R2 PC(H) PC(L)

Numbering of bits Subfields (Divided into two parts)

• Often we want the transfer to occur only under a predetermined
control condition.
if (p=1) then (R2  R1)
where p is a control signal generated in the control section.
• In digital systems, this is often done via a control signal, called
a
control function
– If the signal is 1, the action takes place
• This is represented as:
P: R2  R1
Which means “if P = 1, then load the contents of register R1
into register R2”, i.e., if (P = 1) then (R2  R1)
 HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS

Implementation of controlled transfer

P: R2  R1

Block diagram Control P Load

R2 Clock
Circuit
n
R1

Timing diagram t t+1

Clock

Load
Transfer occurs here

• The same clock controls the circuits that generate the

control function and
the destination register
• Registers are assumed to use positive-edge-triggered flip-
flops
 SIMULTANEOUS OPERATIONS
• If two or more operations are to occur simultaneously, they
are separated with commas
P: R3  R5, MAR  IR
• Here, if the control function P = 1, load the contents of R5
into R3, and at the same time (clock), load the contents of
register IR into register MAR

BASIC SYMBOLS FOR REGISTER TRANSFERS

Symbols Description Examples
Capital letters Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)
Arrow  Denotes transfer of information R2  R1
Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A  B, B  A
 Bus and Memory Transfers

BUS AND MEMORY TRANSFERS

Bus is a path(of a group of wires) over which information is transferred,

from any of several sources to any of several destinations.
From a register to bus: BUS  R

Register A Register B Register C Register D

Bus lines

Register A Register B 1 Register C Register D 1

2 3 4 2 3 4
1 2 1 2 3 4
3 4
B1 C1 D1 B2 C2 D2 B3 C3 D3 B4 C4 D 4
0 0 0 0
4 x1 4 x1 4 x1 4 x1
MUX MUX MUX MUX

x
select
y

4-line bus
 Bus and Memory Transfers

TRANSFER FROM BUS TO A DESTINATION REGISTER

Bus lines

Load
Reg. R0 Reg. R1 Reg. R2 Reg. R3

D0 D1 D2 D3
Select z E (enable)
w 2x4
Decoder

Three-State Bus Buffers

Output Y=A if C=1
Normal input A
High-impedence if C=0
Control input C

Bus line with three-state buffers

Bus line for bit 0
A0
B0
C0
D0

S0 0
Select 1
S1 2
Enable 3
 Bus and Memory Transfers

BUS TRANSFER IN RTL

• Depending on whether the bus is to be
mentioned explicitly or not, register transfer can
be indicated as either
R2  R1
or
BUS  R1, R2  BUS
• In the former case the bus is implicit, but in the
latter, it is explicitly indicated
 Bus and Memory Transfers

MEMORY (RAM)
• Memory (RAM) can be thought as a sequential circuits
containing some number of registers
• These registers hold the words of memory
• Each of the r registers is indicated by an address
• These addresses range from 0 to r-1
• Each register (word) can hold n bits of data
• Assume the RAM contains r = 2k words. It needs the following
– n data input lines
data input lines
– n data output lines
– k address lines n

– A Read control line address lines

k RAM
– A Write control line Read
unit
Write
n
data output lines
 Bus and Memory Transfers
MEMORY TRANSFER
• Collectively, the memory is viewed at the register level
as a device, M.
• Since it contains multiple locations, we must specify
which address in memory we will be using
• This is done by indexing memory references
• Memory is usually accessed in computer systems by
putting the desired address in a special register, the
Memory Address Register (MAR, or AR)
• When memory is accessed, the contents of the MAR
get sent to the memory unit’s address lines
M
Memory Read
AR
unit Write

Data out Data in

 Bus and Memory Transfers
MEMORY READ
• To read a value from a location in memory and load it into a register, the
register transfer language notation looks like this:
R1  M[MAR]
This causes the following to occur
– The contents of the MAR get sent to the memory address lines
– A Read (= 1) gets sent to the memory unit
– The contents of the specified address are put on the memory’s output data lines
– These get sent over the bus to be loaded into register R1

MEMORY WRITE
• To write a value from a register to a location in memory looks like this in
register transfer language:
M[MAR]  R1
This causes the following to occur
– The contents of the MAR get sent to the memory address lines
– A Write (= 1) gets sent to the memory unit
– The values in register R1 get sent over the bus to the data input lines of the
memory
– The values get loaded into the specified address in the memory
 Bus and Memory Transfers

SUMMARY OF REGISTER TRANSFER MICROOPERATIONS

AB Transfer content of reg. B into reg. A

AR  DR(AD) Transfer content of AD portion of reg. DR into reg.
A  constant AR Transfer a binary constant into reg. A
ABUS  R1, Transfer content of R1 into bus A and, at the same
R2  ABUS time, Transfer content of bus A into R2
AR Address register
DR Data register
M[R] Memory word specified by reg. R
M Equivalent to M[AR]
DR Memory read operation:
 transfers content of
memory word specified
M by AR into DR
Memory write operation: transfers content of
M DR into memory word specified by AR

ARITHMETIC MICROOPERATIONS

Computer system microoperations are of four types:

1. Register transfer microoperations transfer binary information from
one register to another
2. Arithmetic microoperations perform arithmetic operations on numeric
data stored in registers.
[Link] microoperations perform bit manipulation operations on non
numeric data stored in registers.
4. Shift microoperations perform shift operations on data stored in
registers.
The basic arithmetic microoperations are
•Addition
•Subtraction
•Increment
•Decrement

The additional arithmetic microoperations are

•Add with carry
•Subtract with borrow
•Transfer/Load
 ARITHMETIC MICROOPERATIONS

Table: Arithmetic Micro-Operations

R3  R1 + R2 Contents of R1 plus R2 transferred to R3

R3  R1 - R2 Contents of R1 minus R2 transferred to R3
R2  R2’ Complement the contents of R2
R2  R2’+ 1 2's complement the contents of R2 (negate)
R3  R1 + R2’+ 1 subtraction
R1  R1 + 1 Increment
R1  R1 - 1 Decrement
 BINARY ADDER / SUBTRACTOR / INCREMENTER

B3 A3 B2 A2 B1 A1 B0 A0
Binary Adder
FA C3 FA C2 FA C1 FA C0

C4 S3 S2 S1 S0

Binary Adder-Subtractor
B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1 C0
FA FA FA FA

C4 S3 S2 S1 S0

A2 A1 A0 1
Binary Incrementer A3

x y x y x y x y
H A H A H A H A
C S C S C S C S

C 4 S 3 S 2 S 1 S 0
 ARITHMETIC CIRCUIT
S1
S0
Cin
A0 X0 C0
S1 D0
S0 FA
B0 0 Y0 C1
1
2
3 4x1
MUX
A1 X1 C1
S1 FA D1
S0 Y1 C2
B1 0 4x1
1 MUX
2
3
A2 X2 C2
S1 FA D2
S0
B2 0 4x1 Y2 C3
1 MUX
2
3
A3 X3 C3
S1 D3
S0 FA
B3 0 4x1 Y3 C4
1 MUX
2
3 Cout
0 1

S1 S0 Cin Y Output Microoperation

0 0 0 B D=A+B Add
0 0 1 B D=A+B+1 Add with carry
0 1 0 B’ D = A + B’ Subtract with borrow
0 1 1 B’ D = A + B’+ 1 Subtract
1 0 0 0 D=A Transfer A
1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A-1 Decrement A
1 1 1 1 D=A Transfer A
 LOGIC MICROOPERATIONS
• It specifies binary operations on the strings of bits stored in registers
– Logic microoperations are bit-wise operations, i.e., they work on
the
individual bits of data
– useful for bit manipulations on binary data
– useful for making logical decisions based on the bit value
A B F0 F1 F2 … F13 F F
14 15

0 0 0 0 0 … 1 1 1
0 1 0 0 0 … 1 1 1
1 0 0 0 1 … 0 1 1
1 1 0 1 0 … 1 0 1
• There are, in principle, 16 different logic functions that can be
defined over two binary input variables
• However, most systems only implement four of these
– AND (), OR (), XOR ( ), Complement/NOT
• The others can be created from combination of these
 Logic Microoperations
LIST OF LOGIC MICROOPERATIONS
• List of Logic Microoperations
- 16 different logic operations with 2 binary vars.
- n binary vars →2 2 n functions

• Truth tables for 16 functions of 2 variables and the corresponding

16 logic micro-operations
x 0011 Boolean Micro-
Name
y 0101 Function Operations
0000 F0 = 0 F0 Clear
0001 F1 = xy F  A  B AND
0010 F2 = xy' F  A  B’
0011 F3 = x FA Transfer A
0100 F4 = x'y F  A’ B
0101 F5 = y FB Transfer B
0110 F6 = x  y FAB Exclusive-OR
0111 F7 = x + y FAB OR
1000 F8 = (x + F  A  B)’ NOR
1001 y)' F  (A  B)’ Exclusive-
1010 F9 = (x  F  B’ NOR
1011 y)' FAB Complement B
1100 F10 = y' F  A’
1101 F11 = x + y' F  A’ B Complement A
1110 F12 = x' F  (A 
F13 = x' + y B)’ NAND
1111 F14 = (xy)' F  all 1's Set to all 1's
F15 = 1
HARDWARE IMPLEMENTATION OF
LOGIC MICROOPERATIONS
Ai 0

Bi
1
4X1
MUX Fi
2

3 Select

S1

S0

Function table
S1 Output -operation
S0
0 F=AB AND
0 F=AB OR
0 F=A XOR
1 B Comple
1 F = A’ ment
0
1
APPLICATIONS OF LOGIC MICROOPERATIONS

• Logic microoperations can be used to manipulate individual

bits or a portions of a word in a register
• Consider the data in a register A. In another register, B, is
bit
• data that will be used to modify A
Selective-set the
 contents
A + B of A
– Selective-complement AAB
– Selective-clear A  A • B’
– Mask (Delete) AA•B
– Clear AAB
– Insert A  (A •
– Compare B) + C
– ... AAB
SELECTIVE SET

• In a selective set operation, the bit pattern in B

is used to set certain bits in A

1100 At
1010 B
1110 (A  A + B)
At+1
• If a bit in B is set to 1, that same position in A
gets set to 1, otherwise that bit in A keeps its
previous value
SELECTIVE COMPLEMENT

• In a selective complement operation, the bit

pattern in B is used to complement certain bits
in A

1100 At
1010 B
0110 (A  A  B)
At+1
• If a bit in B is set to 1, that same position in A
gets complemented from its original value,
otherwise it is unchanged
SELECTIVE CLEAR

• In a selective clear operation, the bit pattern in

B is used to clear certain bits in A

1100 At
1010 B
0100 (A  A 
At+1
B’)
• If a bit in B is set to 1, that same position in A
gets set to 0, otherwise it is unchanged
MASK OPERATION
• In a mask operation, the bit pattern in B is
used to clear certain bits in A

1100 At
1010 B
1000 At+1 (A  A 
B)
• If a bit in B is set to 0, that same position in A
gets set to 0, otherwise it is unchanged
CLEAR OPERATION

• In a clear operation, if the bits in the same

position in A and B are the same, they are
cleared in A, otherwise they are set in A

1100 At
1010 B
0110 At+1 (A  A  B)
INSERT OPERATION
• An insert operation is used to introduce a specific bit pattern into A
register, leaving the other bit positions unchanged
• This is done as
– A mask operation to clear the desired bit positions, followed by
– An OR operation to introduce the new bits into the desired
positions

Example
Suppose 1101
you wanted
1000 1011
to introduce
0001 1010
A (Original)
into the low order four bits
of A: 1101 1000 1011 1010 A (Desired)

1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask
1101 1000 1011 0000 A(Intermediate)
0000 0000 0000 1010 Added bits

1101 1000 1011 1010 A (Desired)

 SHIFT MICROOPERATIONS
• Shift microoperations are used for serial transfer of data.
• The information transferred through the serial input determines
the type of shift. There are three types of shifts
– Logical shift
– Circular shift
– Arithmetic shift
• A right shift operation
Serial
input

• A left
shift
operatio
n
Serial
input
LOGICAL SHIFT
• In a logical shift the serial input to the shift is a 0.
• A right logical shift operation:
0

• A left logical shift operation:

0

• In a Register Transfer Language, the following notation

is used
– shl for a logical shift left
– shr for a logical shift right
– Examples:
• R2  shr R2
• R3  shl R3
CIRCULAR SHIFT
• In a circular shift the serial input is the bit that is shifted
out of the other end of the register.

• A right circular shift operation:

• A left circular shift operation:

• In a RTL, the following notation is used

– cil for a circular shift left
– cir for a circular shift right
– Examples:
• R2  cir R2
• R3  cil R3
 ARITHMETIC SHIFT
• An arithmetic shift is meant for signed binary numbers
(integer)
• An arithmetic left shift multiplies a signed number by
two
• An arithmetic right shift divides a signed number by
two
• The main distinction of an arithmetic shift is that it must keep
the sign of the number the same as it performs the
multiplication
signor division
bit

A right arithmetic shift operation:

0
sign
bit

A left arithmetic shift operation:

 ARITHMETIC SHIFT
• An left arithmetic shift operation must be
checked for the overflow
0
sign
bit

Before the shift, if the leftmost two

V bits differ, the shift will result in an
overflow

• In a RTL, the following notation is used

– ashl for an arithmetic shift left
– ashr for an arithmetic shift right
– Examples:
• R2  ashr R2
• R3  ashl R3
HARDWARE IMPLEMENTATION OF
SHIFT MICROOPERATIONS

Serial 0 for shift right (down)

Select 1 for shift left (up)
input (IR)

S
MUX H0
0
1
A0

A1 S
MUX H1
0
A2 1

A3
S
MUX H2
0
1

S
MUX H3
0
1

Serial
input (IL)
ARITHMETIC LOGIC SHIFT UNIT
S3
S2
S1 Ci
S0

Arithmetic Di
Circuit
Select
0 4x1
Ci+1 1 MUX Fi
2
3

Bi Logic Ei
Ai Circuit
shr
Ai-1
Ai+1 shl

S3 S2 S1 S0 Cin Operation Function

0 0 0 0 0 F=A Transfer A
0 0 0 0 1 F=A+1 Increment A
0 0 0 1 0 F=A+ Addition
0 0 0 1 1 B Add with
0 0 1 0 0 F=A+ carry
0 0 1 0 1 B+1 Subtract with borrow
0 0 1 1 0 F=A+ Subtraction
0 0 1 1 1 B’ Decrement A
0 1 0 0 X F = A + B’+ 1 TransferA
0 1 0 1 X F=A-1 AND
0 1 1 0 X F=A OR
0 1 1 1 X F = AB XOR
1 0 X X X F =A B Complement A
1 1 X X X F=AB Shift right A into F
F = A’ Shift left A into F
F = shr A
 Instruction Codes
• Every different processor type has its own design (different
registers, buses, microoperations, machine instructions, etc)
• Modern processor is a very complex device
• It contains
– Many registers
– Multiple arithmetic units, for both integer and floating
point
calculations
– Etc.
• However, to understand how processors work, we will start with
a simplified processor model
• This is similar to what real processors were like ~25 years ago
• M. Morris Mano introduces a simple processor model he calls
the Basic Computer
 THE BASIC COMPUTER

• The Basic Computer has two components, a processor and

memory
• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in
memory
• Each word is 16 bits long
0
CPU

RAM

15 0

4095
 Instruction codes
INSTRUCTIONS
• Program
– A sequence of (machine) instructions
• (Machine) Instruction- are in the form of binary codes known
as instruction codes.
– A group of bits that tell the computer to perform a specific
operation (a sequence of micro-operation)
• The instructions of a program, along with any needed data are
stored in memory
• Each instruction can be divided into different fields.
- Operation code
- Source/destination Operand
- Source Operand address
- Destination Operand address
- Next Instruction address
• Types of operands
- Addresses, Numbers, characters, logical data
 Instruction codes
INSTRUCTION FORMAT
• A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for that
instruction
– An address that specifies the registers and/or locations in
memory to use for that operation
• In the Basic Computer, since the memory contains 4096 (= 212) words,
we needs 12 bit to specify which memory address this instruction will
use
• In the Basic Computer, bit 15 of the instruction specifies the
addressing mode (0: direct addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits
long, that leaves 3 bits for the instruction’s opcode

Instruction Format for immediate Instruction Format for direct and indirect
operand address
15 14 12 11
15 12 11 0 I Opcode Address 0
Opcode Address
Addressing
Addressing mode
mode
 Instruction codes
ADDRESSING MODES
• The address field of an instruction can represent either
– Direct address: the address in memory of the data to use
(the address of the operand), or
– Indirect address: the address in memory of the address in
of the data to use
memory Direct addressing Indirect addressing

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand

1350 Operand

+ +
AC AC

• Effective Address (EA)

– The address, that can be directly used without modification to
access an operand for a computation-type instruction, or as
the target address for a branch-type instruction
 Addressing Modes

• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement (Indexed)
• Stack
Immediate Addressing
• Operand is part of instruction
• Operand = address field
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range

Instruction
Opcode Operand
Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space
Instruction
Opcode Address A
Memory

Operand
Indirect Addressing
• Memory cell pointed to by address field contains the
address of (pointer to) the operand
• EA = (A)
– Look in A, find address (A) and look there for operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to
accumulator
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded
– e.g. EA = (((A)))
• Draw the diagram yourself
• Multiple memory accesses to find operand
• Hence slower
Indirect Addressing Diagram

Instruction
Opcode Address A
Memory
Pointer to operand

Operand
Register Addressing
• Operand is held in register named in address filed
• EA = R
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch
• No memory access
• Very fast execution
• Very limited address space
• Multiple registers helps performance
– Requires good assembly programming or compiler
writing
– N.B. C programming
• register int a;
• c.f. Direct addressing
Register Addressing Diagram

Instruction
Opcode Register Address R
Registers

Operand
Register Indirect Addressing
• C.f. indirect addressing
• EA = (R)
• Operand is in memory cell pointed to by contents of register R
• Large address space (2n)
• One fewer memory access than indirect addressing

Instruction
Opcode Register Address R
Memory

Registers

Pointer to Operand Operand

Displacement Addressing
• EA = A + (R)
• Address field hold two values
– A = base value
– R = register that holds displacement
– or vice versa
Instruction
Opcode Register R Address A
Memory

Registers

Pointer to Operand Operand

+
Relative Addressing
• A version of displacement addressing
• R = Program counter, PC
• EA = A + (PC)
• i.e. get operand from A cells from current location pointed to
by PC
• c.f locality of reference & cache usage

Base-Register Addressing
• A holds displacement
• R holds pointer to base address
• R may be explicit or implicit
• e.g. segment registers in 80x86
Indexed Addressing
• A = base
• R = displacement
• EA = A + (R)
• Good for accessing arrays
– EA = A + (R)
– R++
y Combinations
• Postindex
EA = (A) + (R)

• Preindex
EA = (A+(R))
• (Draw the diagrams)
Stack Addressing
• Operand is (implicitly) on top of stack
• e.g.
– ADD Pop top two items from stack and add
Pentium Addressing Modes
• Virtual or effective address is offset into segment
– Starting address plus offset gives linear address
– This goes through page translation if paging enabled
• 12 addressing modes available
– Immediate
– Register operand
– Displacement
– Base
– Base with displacement
– Scaled index with displacement
– Base with index and displacement
– Base scaled index with displacement
– Relative
 Instruction codes

PROCESSOR REGISTERS
• A processor has many registers to hold instructions,
addresses, data, etc
• The processor has a register, the Program Counter (PC) that holds
the memory address of the next instruction to get
– Since the memory in the Basic Computer only has 4096
locations, the PC only needs 12 bits
• In a direct or indirect addressing, the processor needs to keep
track of what locations in memory it is addressing: The Address
Register (AR) is used for this
– The AR is a 12 bit register in the Basic Computer
• When an operand is found, using either direct or indirect
addressing, it is placed in the Data Register (DR). The
processor then uses this value as data for its operation
• The Basic Computer has a single general purpose register – the
Accumulator (AC)
 Instruction codes
PROCESSOR REGISTERS
• The significance of a general purpose register is that it can be
referred to in instructions
– e.g. load AC with the contents of a specific memory location; store
the contents of AC into a specified memory location
• Often a processor will need a scratch register to store
intermediate results or other temporary data; in the Basic
Computer this is the Temporary Register (TR)
• The Basic Computer uses a very simple model of input/output
(I/O) operations
– Input devices are considered to send 8 bits of character data to
the processor
– The processor can send 8 bits of character data to output devices
• The Input Register (INPR) holds an 8 bit character gotten from an
input device
• The Output Register (OUTR) holds an 8 bit character to be send to
an output device
 Registers
COMPUTER REGISTERS
Registers in the Basic Computer

11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR or MDR 16 Data Register Holds memory operand
AR or MAR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds the data read from i/p device
OUTR 8 Output Register Holds the data to be sent to the o/p device
 Registers

COMMON BUS
SYSTEM
• The registers in the Basic Computer are
connected using a bus
• This gives a savings in circuitry over
complete connections between registers
 Registers
COMMON BUS SYSTEM
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write
Read AR 1

LD INR CLR
PC 2 S2 S1 S0 Register
LD INR CLR 0 0 0 x
0 0 1 AR
DR 3 0 1 0 PC
0 1 1 DR
LD INR CLR
1 0 0 AC
E 1 0 1 IR
ALU AC 4 1 1 0 TR
1 1 1 Memory
LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
 Registers

COMMON BUS
SYSTEM
Read
INPR
Memory Write
4096 x 16 S2 S1 S0 Register
E ALU 0 0 0 x
Address
0 0 1 AR
0 1 0 PC
0 1 1 DR
AC 1 0 0 AC
1 0 1 IR
L I C 1 1 0 TR
1 1 1 Memory
L I C L

L I C DR IR L I C

PC TR

AR OUTR LD

L I C

7 1 2 3 4 5 6

16-bit Common Bus

S0 S1 S2
 Registers
COMMON BUS SYSTEM
• Three control lines, S2, S1, and S0 control which register
the bus selects as its input
S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

• Either one of the registers will have its load signal activated,
or the memory will have its read signal activated
– Will determine where the data from the bus gets
loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto the
bus in the high order 4 bit positions
• When the 8-bit register OUTR is loaded from the bus, the
data comes from the low order 8 bits on the bus
 Instructions

COMPUTER INSTRUCTIONS

• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~

110)
I Opcode Address
15 14 12 11 0

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1
Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 0
1 1 1 I/O operation
12
1 11
 Instructions
BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol I=0 I=1 Description

AND 0xxx 8xxx AND memory word to

ADD 1xxx 9xxx AC Add memory word to
LDA 2xxx Axxx AC Load AC from
STA 3xxx Bxxx memory
BUN 4xxx Cxxx Store content of AC into
BSA 5xxx Dxxx memory
ISZ 6xxx Exxx Branch unconditionally
Branch and save return address
Increment and skip if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and
CIL 7040 E
INC 7020 Circulate left AC and E
SPA 7010
SNA Increment AC
SZA 7008 Skip next instr. if AC is positive
SZE 7004 Skip next instr. if AC is
HLT 7002 negative Skip next instr. if AC
7001 is zero Skip next instr. if E is
zero
Halt computer
INP F800 Input character to AC
OUT F400 Output character from
SKI F200 AC Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
Example Memory reference Instructions
AND
AC  AC X M[AR]
ADD
AC AC + M[AR]
LDA
AC  M[AR]
STA
M[AR]  AC
BUN
PC  AR
BSA
M[AR]  PC, PC  PC+1
ISZ
DR M[AR]
DR  DR+1
M[AR]  DR
If(DR=0)
then PC 
PC+1
 Instructions
INSTRUCTION SET COMPLETENESS
A computer should have a set of instructions so that the
user can construct machine language programs to evaluate
any function that is known to be computable.
• Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main
memory and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT
 Instruction codes
CONTROL UNIT
• Control unit (CU) of a processor translates from machine
instructions to the control signals for the microoperations that
implement them

• Control units are implemented in one of two ways

• Hardwired Control
– CU is made up of sequential and combinational circuits to
generate the control signals
• Microprogrammed Control
– A control memory on the processor contains microprograms
that activate the necessary control signals

• We will consider a hardwired implementation of the control unit

for the Basic Computer
 Timing and control
TIMING AND CONTROL
Control unit of Basic Computer

Instruction register (IR)

15 14 13 11 - 0 Other inputs
12

3x8
decoder
7 6543
210
D0
I Combinational
D7 Control Control
signals
logic

T15

T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock
 Timing and control
TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.

D3T4: SC 

C l oTc0k
0 T1 T2 T3 T4 T0

T0

T1

T2

T3

T4

D3

CLR
SC
 INSTRUCTION CYCLE
• In Basic Computer, a machine instruction is executed in the
following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the
instruction has an indirect address
4. Execute the instruction
• After an instruction is executed, the cycle starts
again at
step 1, for the next instruction

• Note: Every different processor has its own (different)

instruction cycle
 Instruction Cycle
FETCH and DECODE
• Fetch and Decode T0: AR  PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2

T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus
 Instrction Cycle
DETERMINE THE TYPE OF INSTRUCTION
Start
SC  

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I
 IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instructi
SC  0 on Execute T4
SC  memory-reference
0 instruction
SC  0

D'7IT3: AR  M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
 MR Instructions
MEMORY REFERENCE INSTRUCTIONS

Symbol Operation Symbolic Description

Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA M[AR] 
ISZ D5
D6 PC, PC 
AR + 1
M[AR]
-The effective address  instruction is in AR and was placed there during timing
of the
signal T2 when I = 0, or during
M[AR] + 1, iftiming signal T3 when I = 1
M[AR] +to1 be
-Memory cycle is assumed = short enough to complete in a CPU cycle
0 then PC 
- The execution of MR
PC+1instruction starts with T4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
 MEMORY REFERENCE INSTRUCTIONS
LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC 
0
BUN: Branch Unconditionally
D4T4: PC  AR, SC 
0
BSA: Branch and SaveMemory,
ReturnPC, AR at time T4 Memory, PC after execution
Address
20 0 BSA 135 20 0 BSA 135
M[AR]  PC, PC  AR +
PC = 21 Next instruction 21 Next instruction
1

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory Memory
 MR Instructions

MEMORY REFERENCE INSTRUCTIONS

BSA:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR 
M[AR] D6T5: DR 
DR + 1
D6T4:
M[AR]  DR, if (DR
= 0) then (PC  PC
+ 1), SC  0
 MR Instructions

FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS

Memory-reference instruction

AND ADD LDA STA

D0T4 D1T4 D3T4

DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0
D2T4
D0T5 D1T5 D2T5
AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4T4 D5T4 D6T4

PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5T5 D6T5
PC  AR DR  DR + 1
SC  0

D6T6
M[AR]  DR
If (DR = 0)
then (PC 
PC + 1)
SC  0
 I/O and Interrupt
INPUT-OUTPUT AND INTERRUPT

A Terminal with a keyboard and a Printer

• Input-Output Configuration
Serial Computer
Input-output communication
terminal interface registers and
flip-flops
Receiver
Printer interface OUTR FGO

AC

Transmitter
Keyboard interface INPR FGI
INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1
bit
- The terminal sends and receives serial information
- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the
computer
 I/O and Interrupt

PROGRAM CONTROLLED DATA TRANSFER

-- CPU -- -- I/O Device --
/* Input */ /* Initially FGI = 0 loop: If FGI = 1 goto loop
*/ loop: If FGI = 0 goto loop INPR  new data,
AC  INPR, FGI  0
FGI  1
/* Output */ /* Initially FGO = 1 loop: If FGO = 1 goto loop
*/ loop: If FGO = 0 goto loop consume OUTR, FGO  1
OUTR  AC, FGO  0

FGI=0 FGO=1
Start Input Start Output

FGI  0
AC  Data

yes yes
FGI=0 FGO=0
no no

AC  INPR OUTR  AC

FGO  0
yes More
Character yes More
Character
n
o no
END
END
INPUT-OUTPUT INSTRUCTIONS
D7IT3 = p
IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off
 I/O and Interrupt

PROGRAM-CONTROLLED INPUT/OUTPUT
• Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware

Input

LOOP, SKI
DEV BUN

LOOP INP

Output DEV

LOOP, LDA DATA

LOP, SKO DEV
BUN LOP
OUT DEV
 INTERRUPT INITIATED INPUT/OUTPUT

- Open communication only when some data has to be passed -->

interrupt.

- The I/O interface, instead of the CPU, monitors the I/O device.

- When the interface founds that the I/O device is ready for data
transfer, it generates an interrupt request to the CPU

- Upon detecting an interrupt, the CPU stops momentarily the task

it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.

* IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions

- when cleared, the computer cannot be interrupted
 I/O and Interrupt
FLOWCHART FOR INTERRUPT CYCLE
R = Interrupt f/f

Instruction cycle =0 =1 Interrupt cycle

R

Fetch and decode Store return address

instructions in location 0
M[0]  PC

Execute =0
IEN
instructions
=1 Branch to location 1
PC  1
=1
FGI
=0
=1 IEN  0
FGO R0
=0
R
1

-The interrupt cycle is a HW implementation of a branch and save return address

operation.
-At the beginning of the next instruction cycle, the instruction that is read from
memory is in address 1.
-At memory address 1, the programmer must store a branch instruction that
sends
the control to an interrupt service routine
- The instruction that returns the control to the original program is "indirect
 I/O and Interrupt

REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE

Memory
Before interrupt After interrupt cycle
0 0 256
1 0 BUN 1120 PC = 0 BUN 1120
1
Main Main
255 Program 255 Program
PC = 256 256
1120 1120
I/O I/O
Program Program

1 BUN 0 1 BUN 0

Register Transfer Statements for Interrupt Cycle

- R F/F  1 if IEN (FGI + FGO)T0T1T2
 T0T1T2 (IEN)(FGI + FGO): R  1
- The fetch and decode phases of the instruction cycle
must be modified Replace T0, T1, T2 with R'T0,
R'T1, R'T2
- The interrupt cycle :
RT0: AR  0, TR
 PC RT1: M[AR]  TR,
PC  0
Data Transfer and Manipulation
Typical data transfer instructions
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

85
Eight addressing modes for the load
instruction
Assembly
Mode Convention Register transfer

Direct address LD ADR AC  M[ADR]

Indirect address LD @ADR AC  M[M[ADR]]
Relative address LD $ADR AC  M[PC + ADR]
Immediate operand LD #NBR AC  NBR
Index addressing LD ADR(X) AC  M[ADR + XR]
Register LD R1 AC  R1
Register indirect LD (R1) AC  M[R1]
Autoincrement LD (R1)+ AC  M[R1], R1  R1 + 1

86
Typical arithmetic instructions

Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with carry ADDC
Subtract with borrow SUBB
Negate (2’s NEG
complement)

87
Typical logical and bit manipulation
instructions
Name Mnemonic
Clear CLR
Complement COM
AND AND
OR OR
Exclusive-OR XOR
Clear carry CLRC
Set carry SETC
Complement carry COMC
Enable interrupt EI
Disable interrupt DI

88
Typical shift instructions

Name Mnemonic
Logical shift right SHR
Logical shift left SHL
Arithmetic shift right SHRA
Arithmetic shift left SHLA
Rotate right ROR
Rotate left ROL
Rotate right through carry
RORC Rotate left through carry
ROLC
89
 Stack Organization

• Stack: A storage device that stores information in such a

manner that the item stored last is the first item retrieved.
• Also called last-in first-out (LIFO) list. Useful for
compound arithmetic operations and nested subroutine
calls.
• Stack pointer (SP): A register that holds the address of the
top item in the stack.
SP always points at the top item in the stack
• Push: Operation to insert an item into the stack.
• Pop: Operation to retrieve an item from the stack.
 REGISTER STACK
A stack can be organized as a collection of a finite
number of registers.
• In a 64-word stack, the stack pointer contains 6
bits.
• The one-bit register FULL is set to 1 when the stack
is full;
EMPTY register is 1 when the stack is empty.
• The data register DR holds the data to be written into
or read from the stack.
The following are the micro-operations associated with
the stack
• Initialization
SP  0, EMPTY  1, FULL  0
Push
SP  SP + 1
M[SP]  DR
If (SP = 0)
then (FULL
 1)
N
o
t
e
 STACK OPERATIONS
REVERSE POLISH NOTATION (postfix)
• Reverse polish notation :is a postfix notation (places operators after operands)
(Example)
Infix notation A+B
Reverse Polish notation AB+ also called postfix.
• A stack organization is very effective for evaluating arithmetic expressions
A * B + C * D  (AB *)+(CD *)  AB * CD * +
( 3 * 4 ) + ( 5 * 6 )  34 * 56 * +
Evaluation procedure:

1. Scan the expression from left to right.

2. When an operator is reached, perform the operation
with the two operands found on the left
side of the operator.
3. Replace the two operands and the operator by the
result obtained from the operation.

(Example)
infix 3 * 4 + 5 * 6 = 42
postfix 3 4 * 5 6 * +

12 5 6 * +
12 30 +
• Reverse Polish notation evaluation with a stack.
Stack is the most efficient way for evaluating arithmetic
expressions.
stack evaluation:
Get value
If value is data: push data
Else if value is operation: pop, pop
evaluate and push.

(Example) using stacks to do this.

3 * 4 + 5 * 6 = 42
=> 3 4 * 5 6 * +
 Instruction Formats
The most common fields in instruction formats are:
1. Mode field: Specifies the way the effective address is determined
2. Operation code: Specifies the operations to be performed.
3. Address field: Designates a memory address or a processor
register
Mode Opcode Address

•Zero address instruction: Stack is used. Arithmetic operation pops two

operands from the stack and pushes the result.
•One address instructions: AC and memory. Since the accumulator always
provides one operand, only one memory address needs to be specified.
•Two address instructions: Two address registers or two memory locations
are specified, one for the final result.
•Three address instructions: Three address registers or memory locations
are specified, one for the final result.
It is also called general address organization.
Zero address instructions
Instruction: ADD
Push and pop operations need to specify one address involved in data transfer.

Stack-organized computer does not use an address field for the instructions ADD, and MUL

Instruction: POP X
Evaluate X = ( A + B ) * ( C + D )

PUSH, and POP instructions need an address field to specify the operand
PUSH A TOS  A
PUSH B TOS  B
ADD TOS  ( A  B)
PUSH C TOS  C
PUSH D TOS  D
ADD TOS  (C  D)
MUL TOS  (C  D) ( A  B)
POP X X  TOS

Advantages: No memory addresses needed during the operation.

Disadvantages: results in longer program codes.
 One address instructions

• One address can be a register name or memory address.

• SINGLE ACCUMULATOR ORGANIZATION
• Since the accumulator always provides one operands, only one memory address
needs to be specified.
Instruction: ADD X
Microoperation: AC  AC + M[X]

LOAD A AC  M [ A]
ADD B AC  AC  M [B]
STORE T
M [T ]  AC

• All operations are done between the AC register and memory operand.
• Advantages: fewer bits are needed to specify the
address. Disadvantages: results in writing long programs.
 Two address instructions

• Assumes that the destination address is the same as that of the

first operand. Can be a memory address or a register name.

• Instruction: ADD R1, R2

Microoperation: R1  R1 + R2
MOV R1, A R1  M [ A]
MOV R2, B R 2  M [B]
ADD R1, R2 R1  R1 R 2
MOV X, R1 M [x]  R1
• most common in commercial computers

• Each address fields specify either a processor register or a memory operand

• Advantages: results in writing medium size programs
• Disadvantages: more bits are needed to specify two addresses.
Three address organization
GENERAL REGISTER ORGANIZATION

• Three address instructions: Memory addresses for the two operands and one
destination need to be specified.

Instruction: ADD R1, R2, R3

Microoperation: R1  R2 + R3

• Advantages: results in writing short programs

• Disadvantages: more bits are needed to specify three addresses.

ADD R1, R2, R3 R1  R 2  R3

Reduced Instruction Set Computer (RISC)
Introduction
• The trend into computer hardware complexity was
influenced by various factors:
– Upgrading existing models to provide more customer
applications
– Adding instructions that facilitate the translation from high-level
language into machine language programs
– Striving to develop machines that move functions from
software implementation into hardware implementation
• A computer with a large number of instructions is
classified
as a complex instruction set computer (CISC).
• A computer use fewer instructions with simple constructs so
they can be executed much faster within the CPU without
having to use memory as often. It is classified as a reduced
instruction set computer (RISC).
99
 Introduction(cont.)
• One reason for the trend to provide a complex
instruction set is the desire to simplify the
compilation and improve the overall computer
performance.
• The essential goal of a CISC architecture is to
attempt to provide a single machine insruction for
each statement that is written in a high-level
language.
• Example of CISC architecture are the DEC VAX
computer and the IBM 37 0computer.

100
 CISC characteristics

• The major characteristics of CISC architecture

are:
– A large number of instructions– typically from 100 to 250
instructions
– Some instructions that perform specialized tasks and are
used infrequently
– A large variety of addressing modes—typically from 5 to
20 different modes
– Variable-length instruction formats
– Instructions that manipulate operands in memory

101
 RISC characteristics
• The major characteristics of a RISC
processor are:
– Relatively few instructions
– Relatively few addressing modes
– Memory access limited to load and store
instructions
– All operations done within the registers of the
CPU
– Fixed-length, easily decoded instruction
format
– Single-cycle instruction execution
– Hardwired rather than microprogrammed 102
 RISC characteristics(cont.)
• Other characteristics attributed to RISC architecture are:
– A relatively large number of registers in the processor unit
– Use of overlapped register windows to speed-up procedure call
and
return
– Efficient instruction pipeline
– Compiler support for efficient translation of high-level language
programs into machine language programs
• Studies that show improved performance for RISC
architecture do not differentiate between the effects of the
reduced instruction set and the effects of a large register
file.
– A large number of registers in the processing unit are sometimes
associated with RISC processors.

103
 Overlapped register windows
• Some computers provide multiple-register banks, and each
procedure is allocated its own bank of registers. This eliminates
the need for saving and restoring register values.
• Some computers use the memory stack to store the parameters
that are needed by the procedure, but this required a memory
access every time the stack is accessed.
• A characteristics of some RISC processors is their use of
overlapped register windows to provide the passing of
parameters and avoid the need for saving and restoring register
values.
• The concept of overlapped register windows is illustrated in Fig.
8-9.

104
 Overlapped register
windows(cont.)
• In general, the organization of register windows will have the
following relationships:
number of global registers = G
number of local registers in each window = L
number of registers common to two windows = C
number of windows = W
• The number of registers available for
each window is
calculated as followed:
window size = L + 2C + G
• The total number of registers needed in
the processor is
register file = (L + C)W + G
• The example of Fig. 8-9:
105
Overlapped register windows
R15
Common to D and A
R10
R73
Local to D
R64
R63
Common to C and D
R58

Proc D R57
Local to C
R48
R47
Common to B and C
R42

Proc C R41
Local to B
R32
R31
R9 Common to A and
Common to all R26
R25
B
procedures Proc B Local to A
R0 R16
R15
Global Common to A and
registers R10
D
Proc A 10
6
 Berkeley RISC I
• The Berkeley RISC I is a 32-bit integrated circuit CPU.
– It supports 32-bit address and either 8-, 16-, or 32-bit
data.
– It has a 32-bit instruction format and a total of 31
instructions.
– There are three basic addressing modes:
• Register addressing, immediate operand, and relative to
PC addressing for branch instructions.
– It has a register file of 138 registers
• 10 global register and 8 windows of 32registers in each
– The 32 registers in each window have an
organization
similar to the one shown in Fig. 8-9.
107
 Berkeley RISC I(cont.)
• Fig. 8-10 shows the 32-bit instruction formats used for
register-to-register instructions and memory access
instructions.
• Seven of the bits in the operation code specify an operation,
and the eighth bit indicates whether to update the status bits
after an ALU operation.
• For register-to-register instructions :
– The 5-bit Rd field select one of the 32 rgisters as a destination for
the result of the operation
– The operation is performed with the data specified in fields Rs
and S2.
– Thus the instruction has a three-address format, but the second
source may be either a register or an immediate operand.

108
 Berkeley RISC I(cont.)
• For memory access instructions:
– Rs to specify a 32-bit address in a register
– S2 to specify an offset
– Register R0 contains all 0’s, so it can be used in any
field to specify a zero quantity
• The third instruction format combines the last three
fields to form a 19-bit relative address Y and is
used primarily with the jump and call instructions.
– The COND field replaces the Rd field for jump
instructions and is used to specify one of 16 possible
branch conditions.

109
Berkeley RISC I instruction formats
31 24 23 19 18 14 13 12 5 4 0

Opcode Rd Rs 0 Not used S2

8 5 5 8 5
1

(a) Register mode: (S2 specifies a register)

31 0
24 23 19 18
Opcode Rd13
14 12 Rs 1 S2

8 5 5 1
13

(b) Register-immediate mode: (S2 specifies an operand )

31 0
24 23 19 18
Opcode COND Y

8 5 19
(c) PC relative mode:
110
 Instruction set of berkeley RISC I
• The 31 instructions of RISC I are listed in
Table8-12.
• They have been grouped into three
categories:
– The data manipulation instructions:
• Perform arithmetic, logic, and shift operations.
• An immediate operand is symbolized by the
number sign #.

ADD R22, R21, R23 R23  R22 + R21

ADD R22, #150, R23 R23  R22 + 150
ADD R0, R21, R22 R22  R21 (Move)
ADD R0, #150, R22 R22  150 (Load immediate)
ADD R22, #1, R22 R22  R22 + 1 (Increment)
111
Instruction set of berkeley RISC I
– The data transfer instructions:
• Consist of six load instructions, three store instructions, and
two instructions that transfer the program status word PSW.
• PSW contains the status of the CPU and includes the
program counter, the status bits from the ALU, pointers used
in conjunction with the register windows, and other info. That
determine the state of the CPU.
LDL (R22)#150, R5  M[R22] + 150
R5 LDL (R22)#0, R5  M[R22]
R5 LDL (R0)#500, R5  M[500]
R5
– The program control instructions:
• Operate with the program counter PC to control the program
sequence
• One uses an index plus displacement addressing
• The second uses a relative to PC mode with the 19-
bit Y value as the
112
relative address
 Instruction set of berkeley RISC I
OpcodeOperands Register transfer Description Data manipulation instructions

ADD Rs,S2,Rd Rd  Rs + S2 Integer add

ADDC Rs,S2,Rd Rd  Rs + S2 + carry Add with carry
SUB Rs,S2,Rd Rd  Rs - S2 Integer subtract
SUBC Rs,S2,Rd Rd  Rs - S2 - carry Subtract with carry
SUBR Rs,S2,Rd Rd  S2 – Rs Subtract reverse
SUBCR Rs,S2,Rd Rd  S2 – Rs – carry Subtract with carry
AND Rs,S2,Rd Rd  Rs S2 AND
OR Rs,S2,Rd Rd  Rs V S2 OR
XOR Rs,S2,Rd Rd  Rs S2 Exclusive-OR
SLL Rs,S2,Rd Rd  Rs shifted by S2 Shift-left
SRL Rs,S2,Rd Shift-right logical
Rd  R s shifted by
SRA Rs,S2,Rd Rd  Rsshifted by S2 Shift-right arithmetic
S2

113
 Instruction set of berkeley RISC I(cont.)

Opcode Operands Register transfer Description

Data transfer instructions

LDL (Rs)s2,Rd Rd  M[Rs + S2] Load long
LDSU (Rs)s2,Rd Rd  M[Rs + S2] Load short
unsigned
LDSS (Rs)s2,Rd Rd  M[Rs + S2] Load short signed
LDBU (Rs)s2,Rd Rd  M[Rs + S2] Load byte unsigned
LDBS (Rs)s2,Rd Rd  M[Rs + S2] Load byte signed
LDHI Rd,Y Rd  Y Load immediate high
STL Rd,(Rs)S2 M[Rs + S2]  Rd Store long
STS Rd,(Rs)S2 M[Rs + S2]  Rd Store short
STB Rd,(Rs)S2 M[Rs + S2]  Rd Store byte
GETPSW Rd Rd  PSW Load status word
PUTPSW Rd PSW  Rd Set status word

114
 Instruction set of berkeley RISC I(cont.)
Opcode Register transfer Description
Operands

Program
JMP control instructions
COND,S2(Rs) PC  Rs + S2 Conditional jump

JMPR COND,Y PC  PC + Y Jump relative

CALL Rd,S2(Rs) Rd  PC Call subroutine

PC  Rs + S2 and
CWP  CWP –1 change window
CALLR Rd,Y Rd  PC Call relative
PC  PC + Y and
CWP  CWP – 1 change window
RET Rd,S2 PC  Rd + S2 Return and
CWP  CWP + 1 change window
CALLINT Rd Rd  PC Disable interrupts
CWP  CWP –1
RETINT Rd,S2 PC  Rd + S2 Enable interrupt
CWP  CWP + 1
GTLPC Rd Rd  PC Get last PC
11
5