Basic Processing Unit
(Control Sequencing)
Internal Block Diagram of a CPU
Fundamental Concepts
• Processor fetches one instruction at a time and perform the operation specified.
• Instructions are fetched from successive memory locations until a branch or a
jump instruction is encountered.
• Processor keeps track of the address of the memory location containing the
next instruction to be fetched using Program Counter (PC).
• Instruction Register (IR)
Executing an Instruction
• Fetch the contents of the memory location pointed to by the PC. The
contents of this location are loaded into the IR (fetch phase).
IR ← [[PC]]
• Assuming that the memory is byte addressable, increment the contents of
the PC by 4 (fetch phase).
PC ← [PC] + 4
(where each instruction comprises 4 bytes)
• Carry out the actions specified by the instruction in the IR (execution
phase).
Processor Organization
Registers:
The processor registers R0 to Rn-1 vary considerably from one
processor to another.
Registers are provided for general purpose used by
programmer.
Registers Y, Z & TEMP are temporary registers used by
processor during the execution of some instruction.
Multiplexer:
Select either the output of the register Y or a constant value 4
to be provided as input A of the ALU.
Constant 4 is used by the processor to increment the contents
of PC.
ALU:
Used to perform arithmetic and logical operation.
Data Path:
The registers, ALU and interconnecting bus are collectively
referred to as the data path.
Register Transfers Riin
Internal Processor Bus
×
Ri
×
Riout
Yin
×
Y
Constant 4
Select MUX
A B
ALU
Zin ×
Z ×
Fig: Input and Ouput Gating for the registers Zout
• The input and output gates for register Ri are controlled by
signals is Rin and Riout .
• If Rin is set to1 - data available on common bus are loaded into
Ri.
• If Riout is set to1 - the contents of register are placed on the bus.
• Riout is set to 0 – the bus can be used for transferring data from
other registers .
Data transfer between two registers:
Transfer the contents of R1 to R4.
1. Enable output of register R1 by setting R1 out=1. This places
the contents of R1 on the processor bus.
2. Enable input of register R4 by setting R4 in=1. This loads
the data from the processor bus into register R4.
Performing an Arithmetic or Logic
Operation
• The ALU is a combinational circuit that has no internal storage.
• ALU gets the two operands from MUX and bus. The result is temporarily
stored in register Z.
• What is the sequence of operations to add the contents of register R1 to
those of R2 and store the result in R3?
1. R1out, Yin
2. R2out, Select Y, Add, Zin
3. Zout, R3in
Fetching a Word from Memory
• Address into MAR; issue Read operation; data into MDR.
Memory-Bus Internal Processor
data Lines Bus
MDRoutE MDRout
× ×
MDR
× ×
MDRinE MDRin
Fig: Connection and Control Signals for Register MDR
Fetching a Word from Memory
The response time of each memory access varies (cache miss, memory-mapped I/O,…).
To accommodate this, the processor waits until it receives an indication that the
requested operation has been completed (Memory-Function-Completed, MFC).
Step Action
• Example: Move R2, (R1) 1 PCout, MARin, Read, Select4, Add, Zin
MAR ← [R1]
2 Zout, Pcin, MDRinE, WMFC
Start a Read operation on the memory
bus 3 MDRout, IRin
Wait for the MFC response from the R1out, MARin, Read
4
memory
Load MDR from the memory bus 5 MDRinE, WMFC
R2 ← [MDR] 6 MDRout, R2in, End
Storing a word in memory
Move (R2), R1 Memory-Bus Internal Processor
• Address is loaded into MAR data Lines Bus
MDRoutE MDRout
• Data to be written loaded into MDR
• Write command is used × ×
Step Action
MDR
1 PCout, MARin, Read, Select4, Add, Zin
2 Zout, Pcin, MDRinE, WMFC
3 MDRout, IRin × ×
4 R2out, MARin
MDRinE MDRin
5 R1out, MDRin, Write
Fig: Connection and Control Signals for Register MDR
6 MDRoutE, WMFC
Execution of a Complete Instruction
• Example: Add R1, (R3)
• Fetch the instruction
• Fetch the first operand (the contents of the memory location pointed to
by R3)
• Perform the addition
• Load the result into R1
Execution of a Complete Instruction
Add R1, (R3) Internal processor
bus
Control signals
Step Action PC
Instruction
Address
1 PCout, MARin, Read, Select4, Add, Zin lines
MAR
decoder and
control logic
Memory
bus
2 Zout, Pcin, MDRinE, WMFC MDR
Data
lines IR
3 MDRout, IRin
Y
Constant 4 R0
4 R3out, MARin, Read
Select MUX
5 R1out, Yin, MDRinE, WMFC Add
A B
ALU Sub R n - 1
control ALU
lines
6 MDRout, SelectY, Add, Zin XOR
Carry-in
TEMP
Z
7 Zout, R1in, End
Figure 7.1. Single-bus organization of the datapath inside a processor.
Question
• Write the control sequence to execute
1. Add the (immediate) number NUM to register R1. [ADD R1, #NUM]
2. Add the contents of memory location NUM to register R1. [ADD R1, 500]
3. Add the contents of memory location whose address is at memory location NUM
to register R1. [ADD R1, (500)]
4. XOR R1, R2
5. AND to AC [AND 500]
6. ADD to AC [ADD 500]
7. Load to AC [LDA 500]
Solution 1
Step Action
1 PCout, MARin, Read, Select4, Add, Zin
2 Zout, Pcin, MDRinE, WMFC
3 MDRout, IRin
4 IR(NUM)out, Yin
5 R1out, SelectY, Add, Zin
Zout, R1in, End
6
Solution 2
Step Action
1 PCout, MARin, Read, Select4, Add, Zin
2 Zout, Pcin, MDRinE, WMFC
3 MDRout, IRin
4 IR(NUM)out, MARin, Read
5 R1out, Yin, MDRinE, WMFC
MDRout, SelectY, Add, Zin
6
7 Zout, R1in, End
Solution 3 Step Action
1 PCout, MARin, Read, Select4, Add, Zin
2 Zout, Pcin, MDRinE, WMFC
3 MDRout, IRin
4 IR(NUM)out, MARin, Read
5 MDRinE, WMFC
MDRout, MARin, Read
6
R1out, Yin, MDRinE, WMFC
7
8 MDRout, SelectY, Add, Zin
9 Zout, R1in, End
Solution 4
Step Action
1 PCout, MARin, Read, Select4, Add, Zin
2 Zout, Pcin, MDRinE, WMFC
3 MDRout, IRin
4 R1out, Yin
5 R2out, SelectY, XOR, Zin
Zout, R1in, End
6
Solution 5 AND to AC [AND 500]
Step Action
1 PCout, MARin, Read, Select4, Add, Zin
2 Zout, Pcin, MDRinE, WMFC
3 MDRout, IRin
4 IR(Addr)out, MARin, Read
5 ACout, Yin, MDRinE, WMFC
MDRout, SelectY, AND, Zin
6
7 Zout, ACin, End
Solution 6 ADD to AC [ADD 500]
Step Action
1 PCout, MARin, Read, Select4, Add, Zin
2 Zout, Pcin, MDRinE, WMFC
3 MDRout, IRin
4 IR(Addr)out, MARin, Read
5 ACout, Yin, MDRinE, WMFC
MDRout, SelectY, ADD, Zin
6
7 Zout, ACin, End
Solution 7 Laod to AC [LDA 500]
Step Action
1 PCout, MARin, Read, Select4, Add, Zin
2 Zout, Pcin, MDRinE, WMFC
3 MDRout, IRin
4 IR(Addr)out, MARin, Read
5 MDRinE, WMFC
MDRout, ACin, End
6
Execution of Branch Instructions
• A branch instruction replaces the contents of PC with the branch target
address, which is usually obtained by adding an offset X given in the
branch instruction.
• The offset X is usually the difference between the branch target
address and the address immediately following the branch instruction.
Execution of Branch Instruction
Step Action
1 PCout, MARin, Read, Select4, Add, Zin
2 Zout, Pcin, Yin, MDRinE, WMFC
3 MDRout, IRin
4 Offset-field-of-IRout, Select Y, Add, Zin
5 Zout, PCin, End
Control sequence for unconditional branch instruction
