DR.

APJ ABDUL KALAM TECHNICAL UNIVERSITY

Branch - ECE
VLSI Design
(KEC-072)
Lecture – 24

Fault Modelling and Design for Testability

By

Dr. Raman Kapoor

Associate Professor
Department of Electronics & Communication Engineering
ABES Engineering College, Ghaziabad
 Fault Modelling at the Logic level
• The most common fault models at this level are (i) Stuck-at fault model and
(ii) Bridging fault model.
• Stuck-At Fault Model: The most common model used for logical faults is the
single stuck-at fault. Here we assume that some of the circuit lines are permanently
fixed at logic-0 or logic-1 due to some failures.
• Bridging Fault Model: A bridging fault is said to have occurred when two or more
signal lines in a circuit are accidentally connected together. It is quite possible due
to imperfection during layout fabrication.
 Switch Level Fault Modelling
• The circuit is defined at the transistor level.
• MOS transistors are considered as switches such that:
– An nMOS transistor is ON when gate is HIGH.
– A pMOS transistor is ON when gate is LOW.
• Types of switch level fault models:
– Stuck-open fault: A transistor never turns ON.
– Stuck-short fault: A transistor is always ON.
 Stuck-Open Fault Modelling
• A transistor becomes non-conducting due to some fault.
• The gate output may depend on its previous state.
– A combinational circuit may exhibit sequential behavior.
• The 2-pattern test which includes two test vectors that are applied in sequence is a
common stuck-open fault model.
 Stuck-Short Fault Modelling
• A transistor is permanently conducting in the presence of fault.
• Both pull-up and pull-down networks may become conducting resulting in large
current flowing from VDD to ground.
• To detect this fault, we monitor the current flowing.
– Known as the IDDQ testing.
– Test vector causes a conducting path from VDD to ground in the presence of fault.
 Design for Testability
• The task of determining whether fabricated chips are fully functional is highly
complex and can be very time-consuming.
• When faulty chips pass an improperly designed test, they can cause system failures
and enormous difficulty in system debugging.
• Thus, it is of great importance to detect faults as early as possible.
• Generating tests for large circuits is very time consuming and ensuring correct
functionality becomes increasingly more difficult.
• If designs can be modified to make test generation easier: “Design for Testability”.
 Design for Testability
• Design for testability (DFT) is a design technique that makes testing a chip
possible and cost-effective by adding additional circuitry to the chip.
• DFT techniques improve the controllability and observability of internal nodes, so
that embedded functions can be tested.
• Most DFT techniques are targeted towards sequential circuits where test generation
is generally a tedious task.
• DFT techniques can be divided into: Ad-hoc techniques, Built-in Self Test, Scan
cell based approach.
 Controllability & Observability
• The controllability of an internal circuit node within a chip is a measure of the ease
of setting the node to a 1 or 0 state.
• Controllability measures the degree of difficulty of testing a particular signal
within a circuit.
• A node with little controllability, such as the most significant bit of a counter,
might require multiple cycles to get it to the right state.
• An easily controllable node would be directly settable via an input pad. For e.g.
making all flip-flops resettable via a global reset signal achieves good
controllability.
 Controllability & Observability
• The observability of a particular circuit node is the degree to which you can
observe the node at the outputs of an integrated circuit (i.e., the pins).
• Observability measures the degree of difficulty of measuring the output of a gate
within a larger circuit to check that it operates correctly.
• The output of an easily observable node will be accessible either directly or with
moderate indirection (i.e., you may have to wait a few cycles).
• The effectiveness of DFT techniques is measured in terms of their impact on
controllability and observability of internal nodes.
 Ad-hoc DFT Techniques
• Ad hoc test techniques, as their name suggests, are collections of ideas aimed at
reducing the testing combinations.
• The common techniques for ad hoc testing include:
– Partitioning large sequential circuits
– Adding test points
– Adding multiplexers
– Providing for easy state reset
• In general, ad hoc testing techniques have been developed based on experience of
designers. While these techniques are still quite valid, increasing chip complexities
require a structural approach to testing.
 Ad-hoc DFT Techniques
• Partition and MUX Technique: Complex circuits can be partitioned and
multiplexers can be inserted such that some of the primary inputs can be fed to
partitioned parts through multiplexers with accessible control signals. This
increases the number of accessible nodes and reduces the number of test patterns.
E.g. Dividing a 32-bit counter into two 16-bit constituents would reduce the testing
time in principle by a factor of 215.
 Ad-hoc DFT Techniques
• Disable Internal Oscillators and Clocks: To avoid synchronization issues during
testing, internal oscillators and clocks should be disabled. For example, rather than
connecting the circuit directly to the on-chip oscillator, the clock signal can be
ORed with a disabling signal followed by an insertion of a testing signal.
 Ad-hoc DFT Techniques
• Avoid Asynchronous and Redundant Logic: The speed of an asynchronous logic
circuit can be faster than that of the synchronous logic circuit but design and
testing is relatively difficult. Additionally, prediction of state transition times is a
challenge.
• The operation of an asynchronous logic circuit is sensitive to input test patterns,
which can often cause RACE condition and result in temporary errors in output
values.
 Ad-hoc DFT Techniques
• Avoid Asynchronous and Redundant Logic: To avoid static hazards, deliberate
redundancy is introduced. However, redundant nodes are difficult to observe since
the dependency of output on redundant node can’t be established. If a fault is
undetectable, the associated line or gate can be removed without changing the
logic function.
 Ad-hoc DFT Techniques
• Avoid Delay Dependent Logic: Chains of inverters can be used to design delay
times and use AND operation of their outputs along with inputs to generate pulses.
Most ATPG programs do not include logic delays to minimize the complexity of
the program. As a result, such delay-dependent logic is viewed as redundant
combinational logic, and the output of the re-convergent gate is always set to
logic-0, which is not correct. Thus, the use of delay-dependent logic should be
avoided.
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