SV-Interfaces

-Geethanjali G
Agenda

 Introduction

 Features
 How Interface Works
 Ports in Interface
 Modports
 Clocking Blocks
 Tasks and Functions in Interfaces
 Parameterized Interfaces
Introduction
 SystemVerilog interface encapsulates communication between blocks.
 An interface allows a number of signals to be grouped together and

represented as a single port.

 Interfaces can have :

- Parameters
- Variables and constants
- Tasks and functions
- initial or always Blocks
- Continuous assignments
Syntax

Simple interface declaration :

interface identifier;
...
interface_items
...
endinterface [ : identifier ]

Device
Device11 interface Device
Device22

(TB)
(TB) (DUT)
(DUT)
How Interfaces Work…
How Interfaces Work Cont…
How Interfaces Work Cont…
Example for Ports in Interface
simple_bus
mem clk cpu

top

interface
interface module
modulemem( mem( module
modulecpu(
cpu(
simple_bus;
simple_bus; simple_bus
simple_bus simple_bus
simple_bus
logic
logicreq,
req,gnt;
gnt; sb,
sb, sb,
sb,
logic
logic[7:0]
[7:0]addr;
addr; input
inputbit
bitclk);
clk); input
inputbit
bitclk);
clk); [Link]
wire
wire [7:0]
[7:0]data;
data; …… ……
logic
logic[1:0]
[1:0]mode;
mode; endmodule
endmodule endmodule
endmodule
logic module
moduletop;
logicstart,
start,rdy;
rdy; top;
endinterface logic
logicclk
clk==0;0;
endinterface
always
always#10 #10clk
clk==! !
clk;
clk;
simple_bus
simple_bussb();sb();
mem
memm1(sb,
m1(sb,clk);
clk);
cpu
cpuc1(sb,
c1(sb,clk);
clk);
endmodule
endmodule
Connecting the Testbench and the Design
Interface Modports
 modport

- System verilog restrict signal access & direction with modport

- Ex:

interface_mod_port.sv

interface mod_if;
logic a, b, c, d;
modport master (input a,b, output c,d);
modport slave (output a,b, input c,d);
endinterface
Tasks and Functions in Interfaces

 SystemVerilog allows tasks and functions to be declared within an interface.

 These tasks and functions are referred to as interface methods.

 If the interface is connected via a modport, the method must be specified using the import

keyword.

interface simple_bus (input bit clk); // Define the interface

logic req, gnt;
logic [7:0] addr, data;
logic [1:0] mode;
logic start, rdy;
task masterRead(input logic [7:0] raddr); // masterRead method
...
endtask: masterRead
Parameterized Interfaces

 Parameters can be used in interfaces to make vector sizes and other

declarations within the interface reconfigurable.

 These values can be changed within the top module.

Ex:

interface simple_bus #(AWIDTH = 8, DWIDTH = 8)

(input bit clk); // Define the interface
logic req, gnt;
logic [AWIDTH-1:0] addr;
logic [DWIDTH-1:0] data;
logic [1:0] mode;
logic start, rdy;
Parameterized Interfaces cont..
task masterRead(input logic [AWIDTH-1:0] raddr); // masterRead method
...
endtask

task slaveRead; // slaveRead method

…
endtask

task masterWrite(input logic [AWIDTH-1:0] waddr);

...
endtask

task slaveWrite;
...
endtask

endinterface: simple_bus
Clocking blocks

Clocking blocks

- An interface can use a clocking block to control timing.

- Creates explicit synchronous timing domains .

- Testbench will always drive the signals at the right time.

- There is one clock per clocking block.

- An interface can contain multiple clocking blocks.

Clocking blocks and modports ex:

interface
interfacearb_if
arb_if(input
(inputbit
bitclk);
clk);
logic
logic[1:0]
[1:0]grant,
grant,request;
request; reset
logic
logicreset;
reset; request[1:0]
grant[1:0]
clocking
clockingcb
cb@(posedge
@(posedgeclk);
clk); clock
input
inputgrant;
grant; ////TB
TBinput
output
input [Link]
outputrequest;
request; ////TB
TBoutput
output
endclocking
endclocking

modport
modportDUTDUT(input
(inputclk,
clk,
input
inputrequest,
request,reset,
reset, ////Design
Designunder
under
test
test
output
outputgrant);
grant);
modport
modportTB TB (clocking
(clockingcb,
cb, ////Synch
Synchsignals
signals
output
outputreset);
reset); ////Async
Asyncsignals
signals
endinterface:
endinterface:arb_if
arb_if
Clocking Declaration
Input Skew: Denotes when an input is sampled before the
clocking event occurs. Input skew is for sampling.

Output Skew: Denotes when an output is synchronized and

sent after the clocking event. Output skew is for driving.

clocking bus @ (posedge clk)

default input #1ns output #2ns // Default skew
input enable, full;
inout data;
output empty;
output reset ; clocking_block.sv
endclocking
Program Block

 It provides an entry point to the execution of testbenches.

 A program block can contain zero or more initial blocks, continuous assignments,

generate , concurrent assertions,data declarations, functions and tasks can be

defined within a program block.

 A program block cannot have hierarchy such as instances of module or interfaces.

program name (<port_list>);

<declarations>; //type,func,class,clocking..
<continuous_assign>
initial <statement_block>
endprogram
Virtual Interfaces

 A virtual interface is a pointer to an actual interface in SystemVerilog.

 It is most often used in classes to provide a connection point to allow classes to

access the signals in the interface through the virtual interface pointer.

 (In other words virtual interface are used to connect between class objects and
modules)

 Virtual interface variables can be arguments of tasks and functions.

 Virtual interface must be initialized before it can be used.

Example