Advanced Digital Design with the Verilog HDL

Dr. Binay Binod Kumar

Department of Electronics and Communication Engineering

VR Siddhartha Academy of Higher Education Deemed to be University

 COURSE OVERVIEW

 Introduction to Logic Design with Verilog

 Structural Models of Combinational Logic
 Verilog Primitives and Design
 Encapsulation Verilog Structural Models
 Module Ports
 Some Language Rules
 Top-Down Design and Nested Modules
 Design Hierarchy and Source-Code
 Organization Vectors in Verilog
 Structural Connectivity
 What is Verilog

Verilog is an HDL (Hardware Description Language). The latest stable version of Verilog
is IEEE 1364-2005. Verilog is a case sensitive language which only uses lowercase. It
supports simulation. In other words, it is possible to create a model of a function and
simulate it before building the real system. The base language of Verilog is C. Therefore,
a programmer who is familiar with C can learn Verilog quickly.

Module is the basic building block in Verilog. It provides information about input and
output ports and hides the internal implementation details. The syntax of module is as
follows. Every Verilog program starts with the keyword “module” and ends with the
keyword “endmodule”.

module <module_name> (input,output);

<program logic>

endmodule
 What is VHDL

VHDL is a Very high speed Integrated circuit HDL that helps to

describe circuits in digital systems. A hardware module in VHDL is
called an entity. The syntax is as follows. The entity starts with
“entity” and ends with “end” keyword.
entity <entity_name> is
port declaration;
end entity_name;

• Non C type.
• In VHDL User defined data types are used.
• In VHDL there is no case sensitive
• More complex
 Verilog Operators

1. Bitwise operators (Unary and Binary)

(a) Unary operators(reduction operators) (used left of

operand)
Y=&a, y=~a, y= ~&a, y=~|a, y= ^a
Eg: a=5'b10101
&a=1'b0 // and all bits
^a = XOR all bits = 1^0^1^0^1
~&a= NAND all bits
~|a = NOR all bits

(b) Binary operators (used between operands)

a= 3'b101, b=3'110
Y= a & b (binary AND=3;b100), a | b (binary OR=3'b111), a ^ b
(binary XOR) (a ~ ^ b)-binary XNOR, (a ~ & b)-binary NAND
 Verilog Operators

2 Arithmetic operators
Five arithmetic operators (+, - * / %)
a=3'b101, b= 3'b100
Y=a+b, a*b, a-b

3. Relational operators
It compares two values and returns either 1 or 0
a= 3'b010, b=3'b100
a> b=1'b0 (false) (is a greater than b)
a <b =1'b1 (true) (is a less than b)
a>= b =1'b0 (is a greater or equal to)
 Language Rules

 Verilog is a case sensitive language (with a few exceptions) ex. Module,

input, output, always, assign, begin, end etc.
 Identifiers: An identifier is a user defined name used to represent
various objects like modules, registers, wires, variables and functions.
Must begin with -upper and lower case letters and underscore
(_)
It may contain - alphabet, digits (0, 1, ..., 9), underscore ( _ )
$ symbol.
Max length of 1024 symbols
 Terminate lines with semicolon
 Single line comments: // A single-line comment goes here
 Multi-line comments: /* nest multi-line comments*/ like this
 Definition

Primitives are predefined logic gates and functional blocks, low-level building
blocks used for gate-level modeling.
n-Input n-Output, 3-state

and buf

nand not

or bufif0

nor bufif1

xor notif0

xnor notif0

keywords are reserved words that defined the language's syntax and semantics.
•config •bufif0
•always •bufif1
•assign •case
•Begin •casex
•buf •casez
 Design Encapsulation

 Encapsulate structural and functional details in a module

 While Verilog doesn't have access specifiers like
SystemVerilog, you can still achieve data hiding to some
extent.
 Internal signals (declared within a module) are not directly
accessible from outside the module. This means that other
modules cannot directly modify the internal state of a module.

module my_design (module_ports);

... // Declarations of ports go here
... // Structural and functional details go here

endmodule
 Encapsulation makes the model available for instantiation in
other modules
 Data Types

Data types is a classification that specify which type of value can

be assigned to the variable.

A Hardware circuit can have one of 4 values

0 = represents logic zero, false condition

1 = represents logic one, true condition
X = unknown logic (can be 1 or 0)
Z = High impedance, floating value

 Two families of data types for variables:

Nets: wire, tri, wand, triand, wor, trior, supply0,

supply1 Registers: reg, integer, real, time,

realtime
 Data Types

Net Data Type : These are used to connect logic gates. It doesn't store
any value on its own.

• In digital logic design mostly wire is used. It is used when there is a

continuous assignment or to drive a circuit. It is most like a electrical
wire to connect 2 components.
• By default all the data types are wire(default value = Z).

Eg: wire a; //single net

wire [2:0] a; // multiple net // a[2], a[1], a[0] combined together.
x_in y wire y1,
1
1 y2;
y_ou
t
nor (y_out, y1, y2);
x_in
and (y1, x_in1, x_in2);
2 y nand (y2, x_in3, x_in4,
x_in 2 x_in5);
3
x_in
4
x_in
5
 Data Types

register Data Type: It is used to represent a variable and can store data between
assignments. So it is used to model hardware registers(constructed from flip- flop)
to store 1 or more bits. Its default value is X and unsigned integer.
Number of bits it can store depends on the system architecture.
Eg: reg a; // store 1 bit // so 1 bit Flip flop
reg [3:0] a ; // store 4 bits // 4 no. of 1 bit flip flop

Integer: It is signed integer variable of 32 bit wide. It's a general purpose register
data type for manipulating quantities.
Its default width is host machine word size(at least 32 bit)
Generally used for counting purpose.
Eg: 0, 4, -43, 53 etc.

real: It stores signed floating point value and rounded off to nearest interger when
assigned to an integer.
Its default value= 0.0
Eg: 5.6, 47.8

time: Its an Unsigned integer variable and 64 bit wide. It is used to store
simulation time during debugging.
Eg : time sim_time; //it stores simulation time in ns.
 Data Types

strings: It is nothing but a sequence of character enclosed in double

quote " ". It is stored in reg variable.
Here each character is 1 byte so reg variable should be large enough to
hold data.

module strings();
reg [8*28:0]string;
// declare a register variable of 28 byte
initial
begin
string="hello verilog world";
$display("%s\n",string);
end
endmodule

Output: hello verilog world

 Structural Models

module module
name ports
primar primar
y y
inputs output module AOI_str (y_out, x_in1, x_in2, x_in3, x_in4,
AOI_str x_in5);
output y_out; port modes
input x_in1, x_in2, x_in3, x_in4,
x_in y x_in5; internal
1 1 wire y1, wires
y_ou
y2; establish
x_in t connectivit
nor (y_out, y1, y2);
2 and (y1, x_in1, x_in2); y
y
and (y2, x_in3, x_in4,
x_in 2 instantiat
x_in5);
endmodule
3 ed
primitives
x_in
4
x_in
5
 Nested Modules
 Model complex structural detail by instantiating modules
within modules

Add_full_0_dela
(a  b) 
c_in y
a. su c_in su
m m
w w3 (a  b) c_in
Add_half_0_dela
a a. sum 1 y c_ou
Add_half_0_dela (ab t
b y b. c_out (a + b) c_in +
)w
a ab
b. c_out 2
b

module Add_half_0_delay (sum, c_out, a,

b);
input a, b;
output sum, c_out;
xor ( sum, a, b);
and (c_out, a, b);
endmodule
Use nested module instantiations to create a top-down design
hierarchy.
 Nested (Cont.)

c_in su module Add_full_0_delay (sum, c_out, a, b,

m c_in);
a Add_full_0_delay input a, b, c_in;
output c_out, module
b c_ou sum; instance name
t wire w1, w2,
w3;
Add_half_0_dela M1 (w1, w2, a, b);
y M2 (sum, w3, c_in,
Add_half_0_dela
or (c_out, w2, w1);
y
w3);
endmodule

The ports of a sub module must be the same order. Or either if we

use .formal name(actual name) in any order.
The instance name of a module is required.
 Port Connection By Name

 Connect ports by name in modules that have several

ports

actual name
Add_half_0_delay ( .b (b),
M1 .c_out
(w2),
.a (a),
formal .sum (w1)
name );
 Vectors in Verilog

 nets or reg data types can be declared as vectors (multiple bit

widths)
 If bit width is not specified, default size is scalar( 1-bit)
 Vectors represent buses
 Vectors are declared by specifying the range [r1: r2]
 where r1 is always the most significant bit (MSB) and r2 is the least
significant bit (LSB).
 Data type [msb:lsb] variable_name

Examples
 wire x,y; //single bit variable
 wire [15:0] data; //16-bit data
 wire [0:31] sum; //MSB is sum[0], LSB is
sum[31]
 reg [7:0] d1,d2,d3; //3 buses of 8-bit width
 reg [1:40] bus; //vector register, 40-bit bus
 Input [3:0]a; // 4 bits a[3], a[2], a[1],a[0]
 Example: 16-bit ripple carry Adder

a[15:0 b[15: c_in

] 0]
16
16

Add_rca_16_0_delay

1
6
c_ou sum[15:
t 0]

a[15:12] b[15:12] a[11:8] b[7:4 a[3:0] b[3:0]

b[11:8] a[7:4] ] c_in

4 4 4 4 4 4 4 4
Add_rca_4 Add_rca_4 Add_rca_4 Add_rca_4
_0_delay _0_delay _0_delay _0_delay
c_ou
t M M M M
4 c_in1 3 c_in 2 c_in 1
2 8 4
Add_rca_16_0_dela
y sum[15:1 sum[11: sum[7: sum[3:
2] 8] 4] 0]
 a b c_in a b

Add_half_0_delay

Add_half_0_dela
y

Add_full_0_delay Add_half_0_dela
y
c_out su c_out
m sum
 Verilog Model: 16-bit ripple carry Adder

module Add_rca_16_0_delay (sum, c_out, a, b,

output
c_in); sum;
[15:0] c_out
output [15:0]
input a,
; b;
input c_in;
wire c_in4, c_in8, c_in12, c_out;

Add_rca_4 M1 (sum[3:0], c_in4, a[3:0], b[3:0], c_in);

Add_rca_4 M2 (sum[7:4], c_in8, a[7:4], b[7:4], c_in4);
Add_rca_4 M3 (sum[11:8], c_in12, a[11:8], b[11:8], c_in8);
Add_rca_4 M4 (sum[15:12] c_out, a[15:12], b[15:12 c_in12)
endmodule , ], ;
module Add_rca_4 (sum, c_out, a, b,
output [3: 0]
c_in); sum;
output c_out;
input [3: 0] a,
input b;
wire c_in
;
c_in
2,
c_in
3,
endmodule c_in
4;

Add_full M1 c_in2, a[0], b[0],

(sum[0], c_in);
Add_full M2 c_in3, a[1], b[1],
(sum[1], c_in2);
Add_full M3 c_in4, a[2], b[2],
(sum[2], c_in3);
Add_full M4 c_out, a[3], b[3],
(sum[3], c_in4);
module Add_full (sum, c_out, a, b, c_in);
output sum,
input c_out; a,
wire b, c_in;
w1, w2,
Add_half M1 (w1,w3;
w2, a, b);
Add_half M2 (sum, w3, c_in, w1);
or M3 (c_out, w2, w3);
endmodule

module Add_half (sum, c_out, a, b);

output sum,
input c_out; a,
b;
xor M1 (sum, a,
and b);
end M2 (c_out, a,
mod b);
ule
Design Hierarchy: 16-bit ripple carry Adder

Add_rca_1
6

M1 M2 M3 M4
Add_rca_4 Add_rca_4 Add_rca_4 Add_rca_4

M1 M2 M3 M4
Add_ful Add_ful Add_ful Add_ful
l l l l

M M M M4
1 2 3
Add_hal Add_hal norf20 invf10
f f 1 1

xo nan no xo nan no
r d t r d t
 STRUCTURAL CONNECTIVITY
 Wires in Verilog establish connectivity between primitives and/or modules
 Data type: nets (Example: wire)
 The logic value of a wire (net) is determined dynamically during simulation
by what is connected to the wire.

MODELING TIP

Use nets to establish structural connectivity.

MODELING TIP
An undeclared identifier is treated by default as a
wire.
 Structural Model: 2-bit Comparator
Compare two 2-bit binary words:

A_lt_B = A1' B1 + A1' A0' B0 + A0'

B1 B0 A_gt_B = A1 B1' + A0 B1' B0'

+ A1 A0 B0'

A_eq_B = A1' A0' B1' B0' + A1' A0

B1' B0 + A1 A0 B1 B0 + A1 A0' B1
B0'

 Classical approach: use K-maps to

reduce the logic and produce the
schematic
 HDL approach: Connect primitives to describe the functionality
implied by the schematic
 Schematic after minimization of K-
maps:

w
A1 6 w
1 A_gt_B
B1
w2
A0 A_lt_B
w
B 7
w3
0

w
4
A_eq_B
w
5
Verilog (Structural) Model:

module compare_2_str (A_gt_B, A_lt_B, A_eq_B, A0, A1, B0,

output A_gt_B, A_lt_B,
B1);
input A_eq_B; A0, A1, B0,
// Note: B1;
w1, w2, … are implicit
wires
nor (A_gt_B, A_lt_B,
or A_eq_B); (A_lt_B, w1,
and w2, w3);
and (A_eq_B, w4, w5);
and (w1, w6, B1);
and (w2, w6, w7, B0); // Note: interchanging w7, B0 and B1 has no
effect
(w
3,
w7,
B0,
endmodule
B1)
;
not

(w
6,
A1)
;
not

(w
 Example: 4-bit Comparator

 Using a structure of 2-bit comparators, form a 4-bit comparator

Note: A strict inequality in the higher order bit-pair determines the relative
magnitudes of the 4-bit words; if the higher-order bit-pairs are equal,
the lower-order bit-pairs determine the output.

Comp_4_str
M1
A3
A1 Comp_2_str
B3 g
B1 t
A3 A2
A0 lt A_gt_B

B3 B2
B0 eq

A2 A_gt_B
M0
B2 A_lt_B
A1
A1 Comp_2_str
A1 Comp_4_str B1 g A_lt_B
A_eq_B B1 t
B1 A0
A0 lt A_eq_B

A0 B0
B0 eq

B0
Verilog Model:

module Comp_4_str (A_gt_B, A_lt_B, A_eq_B, A3, A2, A1, A0, B3, B2, B1,
output A_gt_B, A_lt_B, A_eq_B;
B0);
input A3, A2, A1, A0, B3, B2, B1,
wire B0;
w1, w0;
Comp_2_str M1 (A_gt_B_M1, A_lt_B_M1, A_eq_B_M1, A3, A2, B3,
B2); Comp_2_str M0 (A_gt_B_M0, A_lt_B_M0, A_eq_B_M0, A1,
A0, B1, B0);
or (A_gt_B, A_gt_B_M1, w1);
and (w1, A_eq_B_M1, A_gt_B_M0);
and (A_eq_B, A_eq_B_M1,
or A_eq_B_M0); (A_lt_B, A_lt_B_M1,
and w0);
endmodulew0, A_eq_B_M1, A_lt_B_M0);
Simulation
Results:
 Logic System

 Four values: 0, 1, x or X, z or Z // Not case sensitive here

 Primitives have built-in logic

 Simulators describe 4-value logic

MODELING TIP

The logic value x denotes an unknown

(ambiguous) value. The logic value z denotes a
high impedance.
Example: 4-Valued Logic

a y
b

x z
a 0 1

b x x z x z x
z z

y x x x
Net Data type
 Net Data type

Note: If one of the input is Z means open circuit its acts as Buffer
 Test Methodology

Task: systematically verify the functionality of a

model. Approaches: Simulation and/or formal
verification Simulation:
(1) detect syntax violations in source code
(2) simulate behavior
(3) monitor results

Design_Unit_Test_Bench
(DUTB)

Stimulus
Generato
r

Unit_Und
er_Test
(UUT)
S
E
T
D
Q

CLR
Q

Respons
e
Monitor
 Example: Testbench

A testbench is a piece of code that generates input signals for the design you want to test.
module
wire
t_Add_half(); sum,
c_out; // Storage containers for stimulus
reg a, b; waveforms
Add_half_0_delay M1 (sum, c_out, a, b);
//UUT
initial begin // Time Out
#100 //
$finish; end Stopwatch

initial begin // Stimulus patterns

#10 a = 0; b // Statements execute in
= 0; sequence
#10 a = 0; b
= 1;
#10 a = 1; b=
0;
#10 a= 1; b =
1;
end
endmodule
 Behaviors for Abstract Models

 Verilog has three types of behaviors for composing abstract models of

functionality

Continuous assignment (Keyword: assign) - later

Single pass behavior (Keyword: initial) – Note: only use in
testbenches Cyclic behavior (Keyword: always) - later
 Single pass and cyclic behaviors execute procedural statements like a
programming language.
 The procedural statements execute sequentially.
 A single pass behavior expires after the last statement executes.
 A cyclic behavior begins executing again after the last statement
executes.
 Signal Generators

 In Verilog, a “behavior” is a group of statements that set values for variables during
simulation — just like hardware would.
 The initial keyword starts a block of code that runs once when the simulation begins
(tsim = 0).
 The statements inside begin ... end are called procedural statements — they run one
by one, in order.
 # delay control operator temporarily suspends execution of a behavior.
 A testbench is a piece of code that generates input signals for the design
you want to test (called the UUT, or Unit Under Test), watches what
happens, and controls how the test runs.
 In the example t_Add_half_0, the inputs are set by the testbench using
variables called reg. This means the values for a and b are controlled by the
testbench code.
Simulation Results for
add_half:
 Event-Driven Simulation

 When a signal value changes in a simulation, it’s called an

“event.”
 But the outputs (sum and c_out) depend on when the input
signals change — just like in a real circuit, where outputs
react to input signals.
 Event-driven simulators only do work when an event
happens — they “sleep” in between events to save time.
 Event-driven simulators update logic values only when
signals change
 Testbench template

Consider the following template as a guide for simple

testbenches:
module t_DUTB_name // substitute the name of the UUT
(); // Declaration of register variables for primary inputs of
reg …; the UUT
wire …; // Declaration of primary outputs of
parameter the UUT time_out = // Provide a value
UUT_name M1_instance_name ( UUT ports go here);

initial $monitor ( ); // Specification of signals to be monitored and

displayed as text

initial #time_out $stop; // (Also $finish) Stopwatch to assure termination of

initial
simulation // Develop one or more behaviors for pattern
generation and/or
begin // error detection

// Behavioral statements generating

waveforms
// to the input ports, and comments
documenting
end // the test. Use the full repertoire of
endmodule behavioral
// constructs for loops and conditionals.
 Representation of Numbers

 Sized numbers specify the number of bits that are to be stored

for a value
 Base b or binary
specifiers:
B d decimal
or D (default) octal
o or hexadecimal
O h
Examples (in-class exercise):
or H

Note Unsized numbers are stored as integers (at least

32 bits)
 Propagation Delay

 Gate propagation delay specifies the time between an input change and
the resulting output change
 In Verilog, by default, gates react instantly (delay = 0). But you can add a
delay to make the simulation more realistic.
 Transport delay describes the time-of-flight of a signal transition
 Verilog uses an inertial delay model for gates and transport delay for nets
 Inertial delay suppresses short pulses (width less than the propdelay value)
 Example: Propagation Delay

Unit-delay simulation reveals the chain of

events

output Add_full
module
sum,
(sum, c_out, a, b,
c_in);
input c_out; a,
wire b, c_in;
w1, w2,
Add_hal w3;
M1 (w1, w2, a, b);
f M2 (sum, w3, w1,
Add_hal c_in); #1 M3 (c_out,
f or w2, w3);
endmodu
le
module Add_half (sum, c_out, a,
output
b); sum, c_out;
input a, b;

xor #1 M1 (sum, a, b); // single delay value

format
and
endmodule #1 M2 (c_out, a, b); // others are possible
 Transport Delay

• Transport delay models pure delay: it passes every input change to the
output, exactly delayed by the specified amount.
• Even very short input pulses always appear at the output — just shifted
in time.
• Used to model ideal wires or transmission lines where all changes
propagate, even glitches.
• Not a built-in Verilog keyword, but this is the behavior you get when you
describe delays with continuous assignments, like:
• assign #5 y = a; // transport delay: output y copies input a with a 5 time
unit delay.
 Inertial Delay

• Inertial delay is more realistic for physical gates.

• Short input pulses that are shorter than the gate’s delay are filtered out —
they do not appear at the output.
• Only pulses longer than the delay make it through.
• In Verilog, this is the default behavior of primitive gates like and, or, not when
you specify delays. Example:
• and #(5) (y, a, b);

Not

x_in Deschedule scheduled

= d
1 tpd =
1 y_out
x_in 2
1
3 1 5
tsim =
4
x_in
=
2 tpd =
6 y_out
x_in 2
2
3 9 2 5 1
1
Truth-Tables Models and User-Defined Primitives

 Till now we have seen standard primitives supported by Verilog such

as AND, OR, NOT, NAND, etc. However, Verilog also provides a facility
to use their own customized primitives commonly known as User-
defined Primitives (UDP).
 Primitives are memory efficient and simulate fast (good for ASIC
libraries)
 User-defined primitives accommodate combinational and sequential
logic
 UDP can not instantiate other modules or primitives.
 UDPs are instantiated similar to gate-level primitives.
 UDP can have multiple input ports but only one output port
 Scalar output and multiple scalar inputs
 Arrange inputs columns of truth table in same order as ports
 Put output in last column, separated by :
 Use a UDP like a built-in primitive
 Table is searched top to bottom until match is found
 z may not be used in table (z in simulation is treated as x)
 No match results in propagation of x
primitive AOI_UDP (y, x_in1, x_in2, x_in3, x_in4,
output y;
x_in5);
input x_in1, x_in2, x_in3, x_in4,
x_in5;
table
// x1 x2 x3 x4 x5
: y 0 0 0 0 0 : 1;
0 0 0 0 1 : 1;
0 0 0 1 0 : 1;
0 0 0 1 1 : 1;
0 0 1 0 0 : 1;
0 0 1 0 1 : 1;
0 0 1 1 0 : 1;
0 0 1 1 1 : 0;

0 1 0 0 0 : 1;
0 1 0 0 1 : 1;
0 1 0 1 0 : 1;
0 1 0 1 1 : 1;
0 1 1 0 0 : 1;
0 1 1 0 1 : 1;
0 1 1 1 0 : 1; An AOI Circuit diagram
0 1 1 1 1 : 0;
10 000:
1;
10 001:
1;
10 010:
1;
10 011:
1;
10 100:
1;
10 101:
1;
10 110:
1;
10 111:
0;

11 000:
0;
11 001:
0;
11 010:
0;
11 011:
0;
11 100:
0;
11 101:
0;
 Example: UDP

selec
t

0
mux_pri mux_ou
1 m t

primitive mux_prim (mux_out, select,

a,output
b); mux_out;
input select, a,
table b;

// select a b :
mux_out
0 0 0 : 0; // Order of table columns = port order of
inputs
0 0 1 : 0 ; // One output, multiple inputs, no inout
0 0 x : 0 ; // Only 0, 1, x on input and output
0 1 0 : 1 ; // A z input in simulation is treated as x
0 1 1 : 1 ; // by the simulator
0 1 x : 1 ; // Last column is the output
// select b :
a mux_out
 1 0 0 : 0;
1 1 0 : 0;
1 x 0 : 0;

1 0 1 : 1;
1 1 1 : 1;
1 x 1 : 1;

x 0 0 : 0; // Reduces pessimism
x 1 1 : 1;

endtable // Note: Combinations not explicitly specified will

endprimitive drive ‘x’
// under simulation.
Alternative model using shorthand notation:

table
// Shorthand notation:
// ? represents iteration of the table entry over the
values 0,1,x.
// i.e., don't care on the input
// select a b : mux_out

// 0 0 ? : 0 ; // ? = 0, 1, x shorthand
notation.
// 0 1 ? : 1;

// 1 ? 0 : 0;
// 1 ? 1 : 1;

// ? 0 0 : 0;
// ?
endtable 1 1 : 1;
 UDPs for Sequential Logic

 In sequential UDP, the current input and the current output value
determine the next output value. The sequential UDP provides an efficient
interface for sequential circuits (i.e. flip-flops and latches) modeling.
 The output has to be declared as reg in sequential UDP
 Output is viewed as next state
 Syntax
 <input1> <input2> <input3> ... <inputN> : <current_state> :
<next_state>;
 Example: Transparent Latch

When enabled, the output follows the input, making it "transparent." When disabled,
the output "latches" or holds its previous value.

primitive latch_rp (q_out, enable,

output q_out;
data);
input enable,
reg data;
q_out;
table
// enable data state q_out/next_state
1 1 : ? : 1;
1 0 : ? : 0;
0 ? : ? : - ; // ‘_’ denotes No Change
// Above entries do not deal with
enable = x.
// Ignore event on enable when data =
state:x 0 : 0 : -;
x 1 : 1 : -;
// Note: The table entry '-' denotes no change of the
output.
endtable
endprimitive
 Example: D-Type Flip-Flop

 Notation for rising edge transition: (01),

(0x), (x1)
 Notation for falling edge transition: (10),
1x), (x0)

data

q_out

output q_out; d_prim1

input clock,
data; clock
reg q_out
;
primitivetable
d_prim1 (q_out, clock, data);
// clk data stat :
: e q_out/next_state
(01) 0 : ? : 0 ; // Rising clock edge
(01) 1 : ? 1;
(0?) 1 : : 1;
1
:

(?0) ? : ? : - ; // Falling or steady clock edge

endtable //
?
endprimitive (??) : ? : - transitions
; // Steady clock, ignore data
 Example: JK-Type Flip-Flop

 Level-sensitive and edge-sensitive behavior can be mixed

in a UDP
 Place level-sensitive behavior a the top of the table

preset
j q_out
J-K Functionality:
- preset and clear override
k clock
clk - no change if j = 0, k = 0
clear
- drive to 1 if j = 1, k = 0
- drive to 0 if j = 0, k = 1
- toggle if j = 1, k = 1
primitive jk_prim (q_out, clk, j, k, preset,
output q_out;
clear);
input clk, j, k, preset,
reg clear; q_out;

table

// clk j k pre clr state q_out/next_state

// Preset
Logic? ? ? 0 1 : ? : 1;
? ? ? * 1 : 1 1;
:
// Clear
?
Logic ? ? 1 0 ? : 0;
:
? ? ? 1 * : 0 : 0;
// Normal
Clocking pre clr state q_out/next_state
// clk j k
r 0 0 0 0 : 0 : 1;
r 0 0 1 1 : ? : - ;
r 0 1 1 1 : ? : 0;
r 1 0 1 1 : ? : 1;
r 1 1 1 1 : 0 : 1;
r 1 1 1 1 : 1 : 0;
f ? ? ? ? : ? : -;

// j and k cases
// clk j pre clr state q_out/next_state
k
b * ? ? : ? : -;
? ? ? : ? : -;
b
// Reduced ?
*
pessimism.
p 0 0 1 1 : ? : -;
p 0 ? 1 ? : 0 -;
:
p ? 0 ? 1 : 1 -;
:
(?0) ? ? ? ? : ? : -;
(1x) 0 0 1 1 : ? : -;
(1x) 0 ? 1 ? : 0 -;
:
 (1x) ? 0 ? 1 : 1 -;
:
x * 0 ? 1 : 1 -;
endtable :
x 0
endprimitive * 1 ? : 0 -;
:

Note: * denotes
any transition,
and is equivalent
to (??)