Paging

CS-502 Operating Systems

Fall 2006
(Slides include materials from Operating System Concepts, 7th ed., by Silbershatz, Galvin, & Gagne and
from Modern Operating Systems, 2nd ed., by Tanenbaum)

CS-502 Fall 2006 Paging 1

 Paging

• A different approach
• Addresses all of the issues of previous topic
• Introduces new issues of its own

CS-502 Fall 2006 Paging 2

 Memory Management
• Virtual (or logical) address vs.
Physical address

• Memory Management Unit (MMU)

– Set of registers and mechanisms to CPU
translate virtual addresses to physical
addresses Logical Addresses
• Processes (and CPU) see virtual MMU
addresses
– Virtual address space is same for all
processes, usually 0 based Physical Addresses
– Virtual spaces are protected from
other processes Memory I/O Devices
• MMU and devices see physical
addresses

CS-502 Fall 2006 Paging 3

 Paging
• Use fixed size units in both
physical and virtual
memory Logical Address Space
(virtual memory)
• Provide sufficient MMU physical memory
hardware to allow units to page 0 frame 0
be scattered across page 1 frame 1
memory page 2 frame 2
• Make it possible to leave page 3 MMU

…
infrequently used parts of

…
virtual address space out frame Y
page X
of physical memory
• Solve internal & external
fragmentation problems
CS-502 Fall 2006 Paging 4
 Paging
• Processes see a contiguous virtual address space
• Memory Manager divides the virtual address
space into equal sized pieces called pages
• Memory Manager divides the physical address
space into equal sized pieces called frames
– Frame size usually a power of 2 between 512 and 8192
bytes
– Frame table
• One entry per frame of physical memory
• State
– Free
– Allocated to one or more processes
• sizeof(page) = sizeof(frame)
CS-502 Fall 2006 Paging 5
 Address Translation for Paging
• Translating virtual addresses
– a virtual address has two parts: virtual page number &
offset
– virtual page number (VPN) is index into a page table
– page table entry contains page frame number (PFN)
– physical address is: startof(PFN) + offset
• Page tables
– Supported by MMU hardware
– Managed by the Memory Manager
– Map virtual page numbers to page frame numbers
• one page table entry (PTE) per page in virtual address space
• i.e., one PTE per VPN

CS-502 Fall 2006 Paging 6

 Paging Translation
logical address
virtual page # offset
physical memory

page
page table frame 0
page
frame 1
physical address
page
page frame # F(PFN) offset frame 2
page
frame 3

…
page
frame Y

CS-502 Fall 2006 Paging 7

 Page Translation Example

• Assume a 32-bit address space

– Assume page size 4KBytes (log2(4096) = 12 bits)
– For a process to address the full logical address space
• Need 220 PTEs – VPN is 20 bits
• Offset is 12 bits
• Translation of virtual address 0x12345678
– Offset is 0x678
– Assume PTE(12345) contains 0x01000
– Physical address is 0x01000678

CS-502 Fall 2006 Paging 8

 PTE Structure
1 1 1 2 20
V R M prot page frame number

• Valid bit gives state of this PTE

– says whether or not a virtual address is valid – in memory and VA range
– If not set, page might not be in memory or may not even exist!
• Reference bit says whether the page has been accessed
– it is set by hardware when a page has been read or written to
• Modify bit says whether or not the page is dirty
– it is set by hardware during every write to the page
• Protection bits control which operations are allowed
– read, write, execute, etc.
• Page frame number (PFN) determines the physical page
– physical page start address

• Other bits dependent upon machine architecture

CS-502 Fall 2006 Paging 9

 Paging – Advantages

• Easy to allocate physical memory

• pick any free frame
• No external fragmentation
• All frames are equal
• Minimal internal fragmentation
• Bounded by page/frame size
• Easy to swap out pages (called pageout)
• Size is usually a multiple of disk blocks
• PTEs maycontain info that help reduce disk traffic
• Processes can run with not all pages swapped in
CS-502 Fall 2006 Paging 10
 Definition — Page Fault
• A trap when a process attempts to reference a
virtual address of a page not in physical memory
• Valid bit in PTE is set to false
• If page exists on disk:–
• Suspend process
• If necessary, throw out some other page (update its PTE)
• Swap in desired page, resume execution
• If page does not exist on disk:–
• Return program error
or
• Conjure up a new page and resume execution
– E.g., for growing the stack!

CS-502 Fall 2006 Paging 11

 Steps in Handling a Page Fault

CS-502 Fall 2006 Paging 12

 Requirement for Paging to Work!

• Machine instructions must be capable of

restarting
• If execution was interrupted during a
partially completed instruction, need to be
able to
– continue or
– redo without harm
• This is a property of all modern CPUs …
– … but not of some older CPUs!
CS-502 Fall 2006 Paging 13
 Note

• Protection bits are important part of paging

• A process may have valid pages that are
• not writable
• execute only
• etc.
• E.g., setting PTE protection bits to prohibit
certain actions is a legitimate way of
detecting the first action to that page.

CS-502 Fall 2006 Paging 14

 Questions?

CS-502 Fall 2006 Paging 15

 Observations

• Recurring themes in paging

– Temporal Locality – locations referenced
recently tend to be referenced again soon
– Spatial Locality – locations near recent
references tend to be referenced soon
• Definitions
– Working set: The set of pages that a process
needs to run without frequent page faults
– Thrashing: Excessive page faulting due to
insufficient frames to support working set
CS-502 Fall 2006 Paging 16
 Paging Issues
• #1 — Page Tables can consume large amounts of space
– If PTE is 4 bytes, and use 4KB pages, and have 32 bit VA space -
> 4MB for each process’s page table
– What happens for 64-bit logical address spaces?

• #2 — Performance Impact
– Converting virtual to physical address requires multiple operations
to access memory
• Read Page Table Entry from memory!
• Get page frame number
• Construct physical address
• Assorted protection and valid checks
– Without fast hardware support, requires multiple memory accesses
and a lot of work per logical address
CS-502 Fall 2006 Paging 17
 Issue #1: Page Table Size
• Process Virtual Address spaces
– Not usually full – don’t need every PTE
– Processes do exhibit locality – only need a subset of the PTEs
• Two-level page tables
• I.e., Virtual Addresses have 3 parts
– Master page number – points to secondary page table
– Secondary page number – points to PTE containing page frame #
– Offset
• Physical Address = offset + startof (PFN)

CS-502 Fall 2006 Paging 18

 Two-level page tables
virtual address

master page # secondary page# offset

physical memory

page
master
physical address frame 0
page table
page frame # offset page
secondary frame 1
secondary page table # page
page table # addr
frame 2
page
frame 3
page frame

…
number

page
frame Y

CS-502 Fall 2006 Paging 19

 12 bits Two-level page tables
8 bits 12 bits
virtual address

master page # secondary page# offset

physical memory

page
master
physical address frame 0
page table
page frame # offset page
secondary frame 1
secondary page table # page
page table # addr
frame 2
page
frame 3
page frame

…
number

page
frame Y

CS-502 Fall 2006 Paging 20

 Note

• Note: Master page number can function as

Segment number
– previous topic

• n-level page tables are possible, but rare in

32-bit systems

CS-502 Fall 2006 Paging 21

 Multilevel Page Tables
• Sparse Virtual Address space – very few secondary PTs
ever needed
• Process Locality – only a few secondary PTs needed at one
time
• Can page out secondary PTs that are not needed now
– Don’t page Master Page Table
– Save physical memory
However
• Performance is worse
– Now have 3 memory access per virtual memory reference or
instruction fetch
• How do we get back to about 1 memory access per VA
reference?
– Problem #2 of “Paging Issues” slide
CS-502 Fall 2006 Paging 22
 Multilevel Page Tables
• Sparse Virtual Address space – very few secondary PTs
ever needed
• Process Locality – only a few secondary PTs needed at one
time
• Can page out secondary PTs that are not needed now
– Don’t page Master Page Table
– Save physical memory
However
• Performance is worse
– Now have 3 memory accesses per virtual memory reference or
instruction fetch
• How do we get back to about 1 memory access per VA
reference?
– Problem #2 of “Paging Issues” slide
CS-502 Fall 2006 Paging 23
 Paging Issues
• Minor issue – internal fragmentation
– Memory allocation in units of pages (also file allocation!)
• #1 — Page Tables can consume large amounts of space
– If PTE is 4 bytes, and use 4KB pages, and have 32 bit VA space -
> 4MB for each process’s page table
– What happens for 64-bit logical address spaces?
• #2 — Performance Impact
– Converting virtual to physical address requires multiple operations
to access memory
• Read Page Table Entry from memory!
• Get page frame number
• Construct physical address
• Assorted protection and valid checks
– Without fast hardware, requires multiple memory accesses and a
lot of work per logical address
CS-502 Fall 2006 Paging 24
 Associative Memory
(aka Dynamic Address Translation — DAT)

VPN # Frame #

• Do fast hardware search of all entries in parallel for VPN

• If present, use page frame number (PFN) directly
• If not,
a) Look up in page table (multiple accesses)
b) Load VPN and PFN into Associative Memory (throwing out
another entry as needed)
CS-502 Fall 2006 Paging 25
 Translation Lookaside Buffer (TLB)

• Associative memory implementation in hardware

– Translates VPN to PTE (containing PFN)
– Done in single machine cycle
• TLB is hardware assist
– Fully associative – all entries searched in parallel with
VPN as index
– Returns page frame number (PFN)
– MMU use PFN and offset to get Physical Address
• Locality makes TLBs work
– Usually have 8–1024 TLB entries
– Sufficient to deliver 99%+ hit rate (in most cases)
• Works well with multi-level page tables
CS-502 Fall 2006 Paging 26
 MMU with TLB

CS-502 Fall 2006 Paging 27

 Typical Machine Architecture

CPU MMU and TLB

live here

Memory
Memory
Memory Bridge Graphics

I/O device I/O device I/O device I/O device

CS-502 Fall 2006 Paging 28

 TLB-related Policies
• OS must ensure that TLB and page tables are consistent
– When OS changes bits (e.g. protection) in PTE, it must invalidate
TLB copy
– If dirty bit is set in TLB, write it back to page table entry
• TLB replacement policies
– Random
– Least Recently Used (LRU) – with hardware help
• What happens on context switch?
– Each process has own page tables (multi-level)
– Must invalidate all TLB entries
– Then TLB fills as new process executes
– Expensive context switches just got more expensive!
• Note benefit of Threads sharing same address space
CS-502 Fall 2006 Paging 29
 Alternative Page Table format – Hashed

• Common in address spaces > 32 bits.

• The virtual page number is hashed into a page

table. This page table contains a chain of VPNs
hashing to the same value.

• Virtual page numbers are compared in this chain

searching for a match. If a match is found, the
corresponding physical frame is extracted

• Still uses TLB for execution

CS-502 Fall 2006 Paging 30
 Hashed Page Tables

CS-502 Fall 2006 Paging 31

 Alternative Page Table format – Inverted

• One entry for each real page of memory.

• Entry consists of virtual address of page stored at
that real memory location, with information about
the process that owns that page.
• Decreases memory needed to store each page
table, but increases time needed to search the table
when a page reference occurs.
• Use hash table to limit the search to one or a few
page-table entries.
• Still uses TLB to speed up execution
CS-502 Fall 2006 Paging 32
 Inverted Page Table Architecture

CS-502 Fall 2006 Paging 33

 Paging – Some Tricks

• Shared Memory
– Part of virtual memory of two or more
processes map to same frames
• Finer grained sharing than segments
• Data sharing with Read/Write
• Shared libraries with eXecute
– Each process has own PTEs – different
privileges

CS-502 Fall 2006 Paging 34

 Shared Pages (illustration)

CS-502 Fall 2006 Paging 35

 Paging trick – Copy-on-write (COW)
• During fork()
– Don’t copy individual pages of virtual memory
– Just copy page tables; all pages start out shared
– Set all PTEs to read-only in both processes
• When either process hits a write-protection fault
on a valid page
– Make a copy of that page for that process, set write
protect bit in PTE to allow writing
– Resume faulting process
• Saves a lot of unnecessary copying
– Especially if child process will delete and reload all of
virtual memory with call to exec()
CS-502 Fall 2006 Paging 36
 Paging – More Tricks
• Memory-mapped files
– Instead of standard system calls (read(), write(),
etc.) map file starting at virtual address X
• I.e., use the file for swap space for that part of VM
– Access to “X + n” refers to file at offset n
– All mapped file PTEs marked at start as invalid
– OS reads from file on first access
– OS writes to file when page is dirty and page is evicted
• Observation
– A great idea when used correctly
– No substitute for structured input & output of
applications

CS-502 Fall 2006 Paging 37

 Paging – Summary
• Partition virtual memory into equal size units
called pages
• Any page can fit into any frame in physical
memory
• No relocation in virtual memory needed by loader
• Only active pages in physical memory at any time
• Supports very large virtual memories and
segmentation
• Hardware assistance is essential
• An dual instance of the fundamental principle of
caching
CS-502 Fall 2006 Paging 38
 Related topic – Caching

CS-502 Fall 2006 Paging 39

 Definition — Cache

• A small subset of active items held in fast

storage while most of the items are in much
larger, slower storage
– Virtual Memory
• Very large, mostly stored on (slow) disk
• Small working set in (fast) RAM during execution
– Page tables
• Very large, mostly stored in (slow) RAM
• Small working set stored in (fast) TLB registers

CS-502 Fall 2006 Paging 40

 Caching is Ubiquitous in Computing

• Transaction processing
• Keep records of today’s departures in RAM while
records of future flights are on disk
• Program execution
• Keep the bytes near the current program counter in
on-chip memory while rest of program is in RAM
• File management
• Keep disk maps of open files in RAM while
retaining maps of all files on disk
• …
CS-502 Fall 2006 Paging 41
 Caching issues
• When to put something in the cache
• What to throw out to create cache space for new
items
• How to keep cached item and stored item in sync
after one or the other is updated
• How to keep multiple caches in sync across
processors or machines
• Size of cache needed to be effective
• Size of cache items for efficiency
• …
CS-502 Fall 2006 Paging 42
 Homework Assignment

• Read (for next week)

– Silbershatz, Chapter 8 and §§9.1 – 9.3

• Programming Project #2 (two weeks)

CS-502 Fall 2006 Paging 43

 Break

Next Topic

CS-502 Fall 2006 Paging 44