MICROCHIP DESIGN

PROCESS
Presented by
Yuvasri G
Introduction
• The microchip design process is a systematic approach to designing and
fabricating integrated circuits (ICs) that combine thousands to billions of
transistors on a single chip.
• This process transforms a conceptual design into a functional microchip used in
devices like smartphones, computers, and IoT systems.
• The VLSI microchip design process can be divided into two main phases: design
(front-end) and fabrication (back-end).
Fabrication
• Oxidation
• Lithography
• Diffusion/Ion Implantation
• Metallization
Oxidation
• Oxidation is the process of growing or depositing a thin layer of silicon
dioxide (SiO₂) on a silicon wafer by exposing it to an oxidizing
environment (typically oxygen or water vapor) at high temperatures .
SiO₂ layer is essential for:
• Insulation: Isolating different components on the chip.
• Gate Dielectric: Forming the insulating layer in MOSFETs
• Masking: Protecting specific areas during doping or etching processes.
• Passivation: Protecting the chip surface from environmental damage .
 Types of Oxidation Processes
Thermal Oxidation
• The silicon wafer is heated in a furnace (800–1200°C) in the presence of an
oxidizing agent, causing a chemical reaction between silicon (Si) and oxygen (O₂)
or water vapor (H₂O) to form SiO₂.
Dry Oxidation:
• Uses pure oxygen.
• Produces a high-quality, dense, and uniform SiO₂ layer.
• Si + O₂ → SiO₂
Wet Oxidation:
• Uses water vapor or steam.
• Less dense than dry oxide
• Si + 2H₂O → SiO₂ + 2H₂
 Types of Oxidation Processes
High-Pressure Oxidation
• High-pressure oxidation is a variation of thermal oxidation where the silicon
wafer is oxidized in a high-pressure environment using oxygen or steam.
• This process accelerates oxide growth.
• Pressure: 10–25 atm.
• Temperature: Lower than standard thermal oxidation (600–900°C).
• Reaction: Same as thermal oxidation (Si + O₂ → SiO₂ or
Si + 2H₂O → SiO₂ + 2H₂)
• but faster due to increased oxidant concentration .
 Types of Oxidation Processes
Plasma Oxidation
• Plasma oxidation is a low-temperature oxidation process that uses a plasma
(ionized gas) to generate reactive oxygen species (e.g., O ⁻, O₂ ⁻) that oxidize the
silicon surface to form SiO₂.
• Temperature: Low (200–400°C), significantly below thermal oxidation.
• Plasma Source: Oxygen gas is ionized using RF (radio frequency) or microwave
energy to create a plasma.
.
Advantages:
• Low Temperature
• Versatility
• Fast Process
 Lithography
• Lithography is the process of defining patterns on a silicon wafer to create the
micro- and nanoscale structures of an IC.
• It uses light (or other forms of energy) to transfer a pattern onto a photosensitive
layer.

Key Role:
• Defines the geometries of transistors, wires, and other components.
• Determines the resolution and critical dimension (CD) of features, critical for
advanced nodes (e.g., 3nm or 2nm).
• Enables high-precision, repeatable patterning across large wafers (e.g., 300mm).
Lithography
Lithography Process
 Optical Replication Process (Optical Lithography)

• Optical replication is another term for optical lithography or photolithography, the most
widely used lithography technique in VLSI.
• It uses light to transfer a pattern from a photomask (a quartz plate with a patterned
chrome layer) onto the photoresist-coated wafer.
• The term “replication” emphasizes the process of copying the mask pattern onto multiple
wafers with high fidelity.
• Light Source: UV (365 nm), DUV (248 nm or 193 nm), or EUV (13.5 nm).
• Resolution: Determined by the wavelength of light (λ) .
• Numerical aperture (NA) of the lens, per the formula:
Resolution = k₁ * λ / NA, where k₁ is a process-dependent factor (~0.25–
0.5).
 Electron Beam Lithography (EBL)

• Electron beam lithography is a maskless lithography technique that uses a focused beam
of electrons to directly write patterns onto a photoresist-coated wafer.

• It is highly precise and used for creating masks or prototyping small-scale, high-
resolution devices in VLSI.

• Energy Source: Electron beam (typically 10–100 keV).

• Resolution: Sub-10 nm, far better than optical lithography due to the short wavelength
of electrons (~0.01–0.1 nm).
 Diffusion

• Diffusion is a process in which dopant atoms (e.g., boron, phosphorus, or arsenic) are
introduced into a silicon wafer and allowed to spread through the crystal lattice by
thermal energy.

Key Role:

• Creates doped regions with precise electrical characteristics (e.g., n-type for phosphorus,
p-type for boron).
• Defines critical device features, such as the source, drain, and channel in MOSFETs.
• Works in conjunction with other processes like oxidation (to form insulating layers or
masks) and lithography (to define where dopants are introduced).
Diffusion Equation
 Key Parameters in Diffusion

Dopant Type:

• N-type dopants: Phosphorus, arsenic, or antimony (add electrons, creating n-type regions).
• P-type dopants: Boron or gallium (add holes, creating p-type regions).
• Diffusion Depth: Controlled by temperature and time (deeper diffusion at higher temperatures or
longer times).
• Temperature: 800–1200°C for thermal diffusion, with higher temperatures increasing the diffusion
rate.
• Diffusion Coefficient (D): Varies with dopant type (e.g., boron diffuses faster than arsenic) and
temperature (D increases exponentially with temperature).
 Ion Implantation
• Ion implantation is a process where dopant atoms (e.g., boron, phosphorus, or arsenic) are ionized,
accelerated, and implanted into a silicon wafer to create regions with specific electrical properties (n-
type or p-type).

The Ion Implantation Process :

• Ionization: Dopant atoms (e.g., boron for p-type, phosphorus or arsenic for n-type) are ionized in a
source chamber, creating positively charged ions (e.g., B ⁺, P ⁺, As ⁺).
• Acceleration: The ions are accelerated through an electric field in an ion implanter, typically at
energies of 1 keV to 1 MeV, depending on the desired implantation depth.
• Implantation: The ion beam is directed at the wafer, penetrating the exposed silicon regions. The
depth and concentration of dopants are controlled by:
1. Energy: Higher energy results in deeper implantation (e.g., 10 keV for shallow junctions, 100 keV
for deeper wells).
2. Dose: The number of ions per unit area (e.g., 10¹³–10¹⁶ ions/cm²), controlling doping concentration.
3. Angle: Tilted implantation (e.g., 7° off-normal) minimizes channeling, where ions travel deep along
crystal planes.
 Ion Implantation

Advantages :

• Precision
• Ultra-Shallow junctions
• Low Lateral Diffusion
• Flexibility
• Compatibility
 Metallization
• Metallization is the process of depositing, patterning, and etching metal layers (e.g.,
aluminum, copper) on a wafer to form interconnects, vias, and contact pads. These metal
structures connect the active devices (e.g., MOSFETs formed via diffusion/ion
implantation) and provide pathways to external pins or packages.

Key Role :
• Creates low-resistance pathways for signal and power distribution.
• Forms contacts between silicon (e.g., source/drain regions) and metal interconnects.
• Enables multi-layer interconnects for complex, high-density chips.
• Impacts chip performance (e.g., speed, power consumption) due to resistance and
capacitance of metal lines.

.
 Metallization
Requirements of Metallization for VLSI Application:

• Low resistivity.

• Ease of pattern generation.

• Mechanical stability.

• No reaction with aluminium.

• Not contaminate devices.

• Provide good device contact.

• Low stress
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