Digital Revolution

Gates
Digital logic
Summary of basic gates
 Boolean Algebra
🞇 Boolean Algebra: is a form of mathematical algebra that is
used in digital logic in digital electronics. Albebra consists of
symbolic representation of a statement (generally
mathematical statements). Similarly, there are expressions,
equations and functions in Boolean algebra as well.

🞇 The main aim of any logic design is to simplify the logic as

much as possible so that the final implementation will
become easy. In order to simplify the logic, the Boolean
equations and expressions representing that logic must be
simplified.

🞇 So, to simplify the Boolean equations and expression, there

are some laws and theorems proposed. Using these laws and
theorems, it becomes very easy to simplify or reduce the
logical complexities of any Boolean expression or function.
 Laws of Boolean Algebra
🞇 The basic rules and laws of Boolean algebraic system
are known as “Laws of Boolean algebra”. Some of the
basic laws (rules) of the Boolean algebra are
🞇 i. Associative law
🞇 ii. Distributive law
🞇 iii. Commutative law
🞇 iv. Absorption law
🞇 v. Consensus law
Associative Law

🞇 Associate Law of Addition

🞇 Statement:
🞇 Associative law of addition states that OR ing
more than two variables i.e. mathematical
addition operation performed on variables will
return the same value irrespective of the
grouping of variables in an equation.
It involves in swapping of variables in groups.
🞇 The Associative law using OR operator can be
written as
🞇 A+(B+C) = (A+B)+C
🞇 Associate Law of Multiplication
🞇 Statement:
🞇 Associative law of multiplication states that
ANDing more than two variables i.e.
mathematical multiplication operation
performed on variables will return the same
value irrespective of the grouping of variables in
an equation.
🞇 The Associative law using AND operator can be
written as
🞇 A * (B * C) = (A * B) * C
Distributive law

🞇 This is the most used and most important law in Boolean

algebra, which involves in 2 operators: AND, OR.
🞇 Statement1:
🞇 The multiplication of two variables and adding the result
with a variable will result in same value as multiplication
of addition of the variable with individual variables.
🞇 In other words, ANDing two variables and ORing the
result with another variable is equal to AND of ORing of
the variable with the two individual variables.
🞇 Distributive law can be written as
🞇 A + BC = (A + B)(A + C)
🞇 This is called OR distributes over AND.
Distributive law

🞇 Proof:
🞇 If A, B and C are three variables then
🞇 A + BC = A * 1 + BC → since A*1 = A
🞇 = A (1 + B)+ BC → since 1 + B = 1
🞇 = A * 1 + AB + BC
🞇 = A *(1 + C) + AB + BC → since A*A = A*1 = A
🞇 = A *(A + C) + B (A + C)
🞇 = (A + C) (A + B)
🞇 A + BC = (A + B) (A + C)
🞇 Hence, distributive law is proved.
Distributive law

🞇 Statement 2:
🞇 The addition of two variables and multiplying the
result with a variable will result in same value as
addition of multiplication of the variable with
individual variables.
🞇 In other words, ORing two variables and ANDing the
result with another variable is equal to OR of ANDing
of the variable with the two individual variables.
🞇 Distributive law can be written as
🞇 A (B+C) = (A B) + (A C)
🞇 This is called AND distributes over OR.
Distributive law

🞇 Proof:
🞇 A (B + C) = A (B*1) + A (C*1) → since 1
* B = B, 1 * C = C
🞇 = [(AB)*(A*1)] + [(AC) *(A*1)]
🞇 =[(AB) * A] + [(AC) *A]
🞇 = (A +1) (AB + AC)
🞇 = (AB +AC) → since 1 + A = 1
🞇 Hence, distributive law is proved.
Commutative law

🞇 Statement:
🞇 Commutative law states that the inter-
changing of the order of operands in a
Boolean equation does not change its
result.
🞇 Using OR operator → A + B = B + A
🞇 Using AND operator → A * B = B * A
🞇 This law is
Absorption laws
🞇 Absorption law involves in linking of a
pair of binary operations.
🞇 i. A+AB = A
🞇 ii. A(A+B) = A
🞇 iii. A+ĀB = A+B
🞇 iv. A.(Ā+B) = AB
🞇 3rd and 4th laws are also called as
Redundancy laws.
Absorption laws proof-1
🞇 Statement 1: A + AB = A
🞇 Proof:
🞇 A + AB = A.1 + AB → since A.1 = A
🞇 =A(1+B) → since 1 + B = 1
🞇 = A.1
🞇=A
Absorption laws proof-2
🞇 Statement 2:A (A + B) = A
🞇 Proof:
🞇 A (A + B) = A.A + A.B
🞇 = A+AB → since A . A = A
🞇 = A (1 + B)
🞇 = A.1
🞇=A
Absorption laws proof-3
🞇 Statement 3:A + ĀB = A + B
🞇 Proof:
🞇 A + ĀB = (A + Ā) (A + B) → since A+BC =
(A+B)(A+C) using distributive law
🞇 = 1 * (A + B) → since A + Ā = 1
🞇 =A + B
🞇 Statement 4: A * (Ā+B) = AB
🞇 Proof: A * (Ā + B) = A. Ā + AB
🞇 = AB → since A Ā = 0
Duality Principle in Boolean algebra

🞇 Statement:
🞇 Duality principle states that “The Dual of the expression can be
achieved by replacing the AND operator with ORoperator, along
with replacing the binary variables, such as replacing 1 with 0
and replacing 0 with 1”.
This law explains that, replacing the variables doesn’t change
the value of the Boolean function.
🞇 But while interchanging the names of the variables, we must
change the binary operators also. “If the operators and variables
of an equation or function that produce no change in the output
of the equation, though they are interchanged is called “Duals”.
🞇 The Duality principle is also known as “De Morgan Duality”,
which states that ‘Interchanging of Duals pairs in Boolean
algebra will result in same output of the equation’.
 Duality theorem

Example:
If we have the Boolean equation like A + B = 0, then the equation
formedby replacing the variable 0 with 1 and replacing the OR operator
with AND operator is A * B = 1. This means both the Boolean functions
are represents the operation of logic circuit.
As per Duality principle, if A, B are two variables then both the equations
A + B = 0 and A * B = 1 are true in case of same logic circuit.
DeMorgan’s Theorem Ist
Statement
DeMorgan’s Theorem IInd
Statement
DeMorgan’s Theorem in Gates
Ist statement
DeMorgan’s Theorem in Gates
IInd statement
Classification Logic gates
3 input AND gate
4 input AND gate
3 input OR gate
4 input OR gate
3 input NAND gate
4 input NAND gate
3 input NOR gate
4 input NOR gate
3 input XOR gate
4 input XOR gate
3 input XNOR gate
4 input XNOR gate
 NAND and NOR

As a universal gates

This presentation is about NAND Logic in the sense of building

other logic gates using just NAND and NOR gates.
What are a Universal Gate
And why NAND and NOR are
known as universal gates?
🞇 A gate which can be use to create any Logic gate
is called Universal Gate

🞇 NAND and NOR are called Universal Gates

because all the other gates can be created by
using these gates
Proof for NAND gates
🞇 Any Boolean function
can be implemented using AND, OR and NOT
gates

🞇 In the same way AND, OR and NOT gates can be

implemented using NAND gates only,
Implementation of NOT using
NAND
A NOT gate is made by joining the inputs of a NAND
gate together.

Desired NOT NAND

Gate Construction
Input Output

0 1

1 0
Implementation of AND using
NAND
🞇 A NAND gate is an inverted AND gate.

🞇 An AND gate is made by following a NAND gate

with a NOT gate Input A Input B Output Q

0 0 0

0 1 0

1 0 0
NAND Construction
1 1 1
Implementation of OR gate using
NAND
• If the truth table for a NAND gate is examined or by
applying De Morgan's Laws, it can be seen that if
any of the inputs are 0, then the output will be 1.
To be an OR gate,

Input A Input B Output Q

0 0 0

0 1 1

1 0 1

NAND 1 1 1
Construction
Implementation of NOR gate
using NAND
🞇 A NOR gate is simply an inverted OR gate. Output
is high when neither input A nor input B is high:

Input A Input B Output Q

0 0 1

0 1 0

1 0 0

1 1 0

NAND
Construction
Implementation of XOR gate
using NAND
🞇 An XOR gate is constructed similarly to an OR
gate, except with an additional NAND
gate inserted such that if both inputs are high,
the inputs to the final NAND gate will also be
high,

Input A Input B Output Q

0 0 0

0 1 1

1 0 1

NAND 1 1 0

Construction
Implementation of XNOR gate using
NAND

• An XNOR gate is simply an XOR gate with an

inverted output:

Input A Input B Output Q

0 0 1

NAND 0 1 0
Construction 1 0 0

1 1 1
Proof for NOR gates
🞇 Like NAND gates, NOR gates are so-called
"universal gates" that can be combined to form
any other kind of logic gate. A NOR gate is
logically an inverted OR gate

Implementation of NOT gate

using NAND Input Output

🞇 NOT made by joining the inputs 0 1

🞇 of a NOR gate. 1 0
Implementation of OR gate using
NOR
• The OR gate is simply a NOR gate followed by
another NOR gate

Input A Input B Output Q

0 0 0 Desired
0 1 1 Gate
1 0 1

1 1 1
Implementation of AND gate
using NOR
• an AND gate is made by inverting the inputs to
a NOR gate.

Input A Input B Output Q

0 0 0

0 1 0

1 0 0

NOR 1 1 1

Construction
Implementation of NAND gate
using NOR

NOR
Construction
Implementation of XOR gate
using NOR
🞇 An XOR gate is made by connecting the output of
3 NOR gates (connected as an AND gate) and the
output of a NOR gate to the respective inputs of a
NOR gate.
Input A Input B Output Q

0 0 0

0 1 1

1 0 1

NOR 1 1 0
Construction
Implementation of XNOR gate using
NOR
🞇 An XNOR gate can be constructed from four NOR
gates implementing the expression "(A NOR N)
NOR (B NOR N) where N = A NOR B". This
construction has a propagation delay three times
that of a single NOR gate, and uses more gates.

Input A Input B Output Q

0 0 1

0 1 0

1 0 0

NOR 1 1 1
Construction
Classification of Logic Families
 87

Classification based on circuit complexity

• Gate/transistor ratio is roughly 1/10

– SSI < 12 gates/chip
– MSI < 100 gates/chip
– LSI < 1K gates/chip
– VLSI < 10K gates/chip
– ULSI < 100K gates/chip
– GSI < 1 Meg gates/chip
 characteristics
⮚ Fan in : The number of inputs that the
gate can handle properly with out
disturbing the output level.

⮚ Fan out : The number of inputs that can

driven simultaneously by the output
with out disturbing the output level.

⮚ Noise immunity : Noise immunity is the

ability of the logic circuit to tolerate the
noise voltage without causing any
unwanted changes in output.
current and voltage parameters of logic ICs

🞇 Gssw
voltage parameters of logic gates
⮚ VILmax : worst case low level input voltage:
Maximum value of input voltage which is
considered as logic 0 level.
⮚ VIHmin : worst case high level input voltage:
Minimum value of input voltage which is
considered as logic 1 level.
⮚ VOLmax : worst case low level output voltage:
Maximum value of output voltage which is
considered as logic 0 level.
⮚ VOHmin : worst case high level output voltage:
Minimum value of output voltage which is
considered as logic 1 level.
current parameters of logic gates
⮚ IIL : low level input current:
It is the current that flows in input when low level
input voltage in specified range is applied
⮚ IIH : high level input current :
It is the current that flows in input when high level
input voltage in specified range is applied
⮚ IOL : low level output current :
It is the current that flows from output when output
voltage in specified range low level is applied
⮚ IOH : high level output current :
It is the current that flows from output when output
voltage in specified range high level is applied
⮚ Noise Margin : The quantative measure of noise
immunity is called noise margin.

⮚ Propagation Delay : The propagation delay of

gate is the average transition delay time for the
signal to propagate from input to output
It is measured in nanoseconds

⮚ Threshold Voltage : The voltage at which the

circuit changes from one state to another state
⮚ Operating Speed : The speed of operation of
the logic gate is the time that elapses between
giving input and getting output.

⮚ Power Dissipation : The power dissipation is

defined as power needed by the logic circuit.
⮚ The power drawn by IC from power supply is
given by: Vcc x Icc
Figure of Merit = Propagation delay time x
power Dissipation

🞇 Operating Temperature:
- The temperature acceptable for
consumer and industrial applications is:
00C to 700C
- For military applications is: -550C to
1250C
- The performance of gates will be in
specified limits of these temperature
ranges.
Resistor Transistor Logic

⮚ RTL is the first logic family which is not

available in monolithic form.

⮚ The basic circuit of the RTL logic family

is the NOR.

⮚ Each input is associated with one

resistor and one transistor.
⮚ The collector of the transistor are tied together at
the output

⮚ The voltage levels for the circuit are 0.2v for the
low level and from 1 to 3.6v for the high level
CIRCUIT DIAGRAM
Truth Table
A B Y=A+B

0 0 1

0 1 0

1 0 0

1 1 0
Working:
⮚ If any input is high. The
corresponding transistor is driven into
saturation and the output goes low,
regardless of the states of the other
transistor.

⮚ If all inputs are low. Then all

transistor are in cutoff state and the
output of the circuit goes high.
Characteristics :

⮚ It has a fan-out of 5.
⮚ Propagation delay is 25 ns.
⮚ Power dissipation is 12 mw.
⮚ Noise margin for low signal input is 0.4
v.
⮚ Poor noise immunity.
⮚ Low speed.
⮚ DTL was first commercial available IC logic family
in 53/73 series.
Diode Transistor Logic(DTL)

⮚ The basic circuit in the DTL logic is the NAND

gate.

⮚ Each input associated with one diode.

⮚ The diode and resistor form an AND gate.

⮚ The transistor services as a NOT gate

 Truth table
A B

Y = A.B
0 0 1
0 1 1
1 0 1
1 1 0
working :-
If any input is low:-
⮚ The corresponding diode conducts
current through Vcc and resistor into the
input node.

⮚ The voltage at point p is equal to the

input voltage + diode drop.
⮚ This is a insufficient voltage for conduction of a
transistor.

⮚ Since the voltage at point p is 0v then the

transistor is cut off state and the output is logic 1.
 If all inputs are high:-
⮚ The transistor is driven into saturation region.

⮚ The voltage at point p is high.

⮚ Hence the output is low.

characteristics :-

⮚ It has fan-out of 8.
⮚ It has high noise immunity.
⮚ Power dissipation is 12mw.
⮚ Propagation delay is average 30ns.
⮚ Noise margin is about 0.7V.
Transistor Transistor Logic(TTL)
⮚ It can perform many digital function and
have achieved the most popularity.

⮚ TTL IC are given the numerical

designation as 5400 and 7400 series

⮚ The basic circuit of TTL with totem pole

output stage is NAND gate
⮚ TTL uses a multi-emitter transistor at the input
and is fast saturation logic circuit.
⮚ The output transistor Q3 and Q4 form a totem-
pole connection.

⮚ This extra output stage is known as totem-pole

stage because three output components Q3 and
Q4 and Diode are stacked on one another.
⮚This arrangement will increase
the speed the speed of operation
and also increase output current
capability.

⮚The function of diode in this

circuit prevent both Q3 and Q4
being turned ON simultaneously .
Circuit Diagram: TTL with Totempole
output
TRUTH TABLE
A B Y=A.B

0 0 1

0 1 1

1 0 1

1 1 0
 Working:-
• A=0,B=0;A=1,B=0;A=0,B=1;
⮚ The emitter base junction of Q1 turns on.

⮚ The collector potential of Q1 falls to 0v,then Q2

turns off.
⮚ Therefore, at point M we have 0volt i.e., the base
voltage of Q2 is 0volt.
⮚ So that, Q2 is also turns off.
▪ But at the same time we have L=+VCC, this voltage
is applied on the base of Q4
⮚ As a result transistor Q3 is turned ON.
⮚ Therefore, the output voltage is given by
V0=+VCC-[Voltage drop in
R4+drop in diode ‘D’]
🞇 A=1,B=1;

⮚ When both input are high then emitter base junction of

transistor Q1 becomes reverse bias. Hence Q1 is turned off.

⮚ However its collector base junction is forward bias,

supplying base current to the transistor Q2. Hence Q2 turns
ON.

⮚ As a result collector potential of Q2 becomes “0” volts.

⮚ Now if L=0volt is applied to the base of Q3, it is turns
off .

⮚ At the same time Q4 is turn ON. Then its collector

potential nearly equal to 0volts.

⮚ Hence the output is low or logic o.

characteristics:-
⮚ TTL has greater speed than DTL.
⮚ Less noise immunity.
⮚ Power dissipation is 10mw.
⮚ It has fan-in of 6 and fan-out of 10.
⮚ Propagation time delay is 5-15nsec.
 EMITTER COUPLED LOGIC
GATE(ECL)
⮚ ECL is non saturated digital logic family.

⮚ The output of ECL provides OR and NOR function.

⮚ Each input is connected to the base of transistor.

⮚ The circuit consists of three parts.
1.differential input amplifier.
2.Internal temperature and voltage compensated bias network.
3.emittor follower output.

⮚ The emitter output requires a pull down resistor for current flow.

⮚ In this logic family we consider the logic 0 as -1.6v and logic 1

as -0.8v.
Truth Table
A B Y=A+B
0 0 1
0 1 0
1 0 0
1 1 0
 working:-
▪ A=0,B=0;
⮚ If all inputs are at low level(-1.6v),the transistor
are turn OFF and Q3 conducts .

⮚ Then at point L the potential is 0volts is applied to

the base of Q5,it is to be turn OFF.

⮚ So, the output of OR gate is logic ‘o’.

⮚ At the same time , the potential at point M= vcc
is applied to the base of Q6,it is to be turn ON.

⮚ So, the output of NOR is at logic 1.

🞇 A=0,B=0,A=0,B=1,A=1,B=0;
⮚ The corresponding transistor is turned ON
and Q3is turned OFF.

⮚ Because its voltage needs at least 0.6v to

start conduction on.

⮚ An input of -0.8v causes the transistor to

conduct and apply -1.6v on the remaining
emitters
⮚ Therefore,Q3 is cut off. The voltage in
resistor R2 flows into the base of
Q5(L=Vcc) then Q5 is turned ON.

⮚ The output is at logic 1.

⮚ At the same time, at point M the

voltage is 0v is applied to the base of
the transistor Q6,it is to be turns off. So,
the NOR output is logic 0.
Characteristics :-
⮚ Propagation delay is very LOW(<1ns)

⮚ ECL is fastest logic family.

⮚ ECL circuit usually operate with –Ve

supplies (+Ve terminal is connected to
ground).
A CMOS inverter
A CMOS gates
A CMOS NAND gates
 Compare TTL and CMOS logic
families
SR. TTL CMOS
NO.
.
1 Transistor –transistor logic. Complementary metal oxide
semiconductor field effect
transistor.
2 Fan out = 10 Fan out = 50

3 Power dissipation 10mw per Power dissipation 0.0125mw per

gate (High) gate (Low)

4 Available functions very high. Available functions high.

5 Propogation delay 10ns. Propogation delay 70ns.

6 Noise Margin 0.4v. Noise Margin o.45 VDD

.

7 Figure of merit 100 pJ. Figure of merit 0.7 pJ.