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8086 modes
The document discusses the minimum and maximum mode systems of the 8086 microprocessor. In minimum mode, the 8086 generates all control signals and a single processor is used. In maximum mode, an external bus controller chip generates control signals and multiple processors can be used. It describes the components, address latching, read and write cycles, and I/O interfacing for both minimum and maximum mode 8086 systems.
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8086 modes
- 1. THE 8086 MICROPROCESSORSIn Minimum & Maximum mode Prepared By pdfshare
- 2. Pin layout ofthe 8086 Prepared By pdfshare
- 3. Minimum-Mode and Maximum- ModeSystem Prepared By pdfshare
- 4. Minimum-Mode and Maximum- ModeSystem (cont.) Signals common to both minimum and maximum mode S4 S3 Function 0 0 Extra segment 0 0 Stack segment 1 0 Code or no segment 1 1 Data segment Prepared By pdfshare
- 5. Minimum-Mode and Maximum- ModeSystem (cont.) Unique minimum-mode signalsPrepared By pdfshare
- 6. Minimum-Mode and Maximum- ModeSystem (cont.) Unique maximum-mode signals Prepared By pdfshare
- 7. Minimum mode 8086system Prepared By pdfshare
- 8. Minimum mode 8086system In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1. In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. The remaining components in the system are latches, transceivers, clock generator, memory and I/O devices. The clock generator also synchronizes some external signal with the system clock. It has 20 address lines and 16 data lines, the 8086 CPU requires three octal address latches and two octal data buffers for the complete address and data separation. Prepared By pdfshare
- 9. Minimum mode 8086system continue… Latches : They are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086. Trans-receivers are the bidirectional buffers and some times they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signals. They are controlled by two signals namely, DEN and DT/R. The DEN signal indicates the availability of valid data over the address/data lines. The DT/R signal indicates direction of data, i.e. from or to the processor. Usually, EPROM are used for monitor storage, while RAM for users program storage. A system may contain I/O devices. Prepared By pdfshare
- 10. Minimum Mode Pins PreparedBy pdfshare
- 11. Status Pins S2S1 S0 Function 0 0 0 Interrupt acknowledge 0 0 1 I/O read 0 1 0 I/O write 0 1 1 Halt 1 0 0 Opcode fetch 1 0 1 Memory read 1 1 0 Memory write 1 1 1 Passive Prepared By pdfshare
- 12. Queue status Prepared Bypdfshare
- 13. Read Bus Cycle(cont.) Minimum-mode memory read bus cycle of the 8086 Prepared By pdfshare
- 14. Minimum mode -READ Hence the timing diagram can be categorized in two parts, the timing diagram for read cycle the timing diagram for write cycle. The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal. During the negative going edge of this signal, the valid address is latched on the local bus. Prepared By pdfshare
- 15. Minimum mode –READ continue… The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal indicates a memory or I/O operation. At T2, the address is removed from the local bus and is sent to the output. The bus is then tri-stated. The read (RD) control signal is also activated in T2. The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus. The addressed device will drive the READY line high. When the processor returns the read signal to high level, the addressed device will again tri-state its bus drivers. Prepared By pdfshare
- 16. Read Bus Cycle(cont.) Minimum-mode memory read bus cycle of the 8086 Prepared By pdfshare
- 17. Minimum mode -Write A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location. The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating). The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write. The M/IO, RD and WR signals indicate the type of data transfer as specified in table below. Prepared By pdfshare
- 18. Maximum mode 8086system Prepared By pdfshare
- 19. Maximum mode 8086system continue… In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground. In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller derives the control signal using this status information . In the maximum mode, there may be more than one microprocessor in the system configuration. The components in the system are same as in the minimum mode system. Prepared By pdfshare
- 20. Maximum mode 8086system continue… The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR ( for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the processor on the status lines. The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by CPU. It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems. Prepared By pdfshare
- 21. Maximum mode continue… AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the MCE/PDEN output depends upon the status of the IOB pin. If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts as peripheral data enable used in the multiple bus configurations. INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device. IORC, IOWC are I/O read command and I/O write command signals respectively . These signals enable an IO interface to read or write the data from or to the address port. The MRDC, MWTC are memory read command and memory write command signals respectively and may be used as memory read or write signals. All these command signals instructs the memory to accept or send data from or to the bus. For both of these write command signals, the advanced signals namely AIOWC and AMWTC are available. Prepared By pdfshare
- 22. Maximum-Mode Interface (cont.) 8288 bus controller Bus status code S2 S1 S0 Function 0 0 0 Interrupt acknowledge 0 0 1 I/O read 0 1 0 I/O write 0 1 1 Halt 1 0 0 Opcode fetch 1 0 1 Memory read 1 1 0 Memory write 1 1 1 Passive Prepared By pdfshare
- 23. Memory Control Signals(cont.) Maximum-mode memory control signals MRDC – Memory Read Command MWTC – Memory Write Command AMWC – Advanced Memory Write Command Prepared By pdfshare
- 24. Read and WriteBus Cycle (cont.) Write cycle Maximum-mode memory write bus cycle of the 8086Prepared By pdfshare
- 25. Read and WriteBus Cycle (cont.) Read cycle Maximum-mode memory read bus cycle of the 8086Prepared By pdfshare
- 26. Isolated Input/Output Interface Minimum-mode interface Minimum-mode 8086 system I/O interface
- 27. Isolated Input/Output Interface(cont.) Maximum-mode interface Maximum-mode 8086 system I/O interface
- 28. Isolated Input/Output Interface(cont.) Maximum-mode interface I/O bus cycle status codes
- 29. Input/Output Bus Cycles(cont.) Input bus cycle of the 8086
- 30. Input/Output Bus Cycles(cont.) Output bus cycle of the 8086
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