VHDL实现PISO移位寄存器的问题

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问题分析： 根据错误信息，可以看到以下几个问题：

• 代码中PISO实体的Q3端口没有驱动器，需要为其提供一个驱动器；
• 代码中PISO实体的D3、D2、D1、D0端口与测试台文件中的D3、D2、D1、D0端口不一致，需要保持一致；
• 编译时出现失败和警告，原因可能是代码中存在错误。

解决方案：

• 修改PISO实体代码，为其添加驱动器：

architecture behavioral of PISO is
    signal D_out : STD_LOGIC_VECTOR(3 downto 0);
    signal Q2 : STD_LOGIC; // 增加一个驱动器
begin
    DFF_3: entity work.D_FF port map (D3, CLK, D_out(3));
    DFF_2: entity work.D_FF port map (D2, CLK, D_out(2));
    DFF_1: entity work.D_FF port map (D1, CLK, D_out(1));
    DFF_0: entity work.D_FF port map (D0, CLK, D_out(0));
 
    Q2 <= D_out(2); // 为Q2提供驱动器

    process (CLK)
    begin
        if rising_edge(CLK) then
            if SHIFT_LOAD = '0' then
                D_out <= D3 & D2 & D1 & D0;
            else
                D_out <= '0' & D_out(3 downto 1);
            end if;
        end if;
    end process;
 
    Q3 <= D_out(3);
end behavioral;

• 修改测试台文件代码，将D3、D2、D1、D0端口与PISO实体代码中的对应端口保持一致：

begin
    dut: PISO
    port map (D0, D1, D2, D3, SHIFT_LOAD, CLK, Q3); // 修改端口连接

    CLK_process: process
    begin
        CLK <= not CLK after 5 ns;
    end process;
 
    stimulus: process
    begin
        wait for 10 ns;
        D3 <= '1'; D2 <= '0'; D1 <= '1'; D0 <= '0'; SHIFT_LOAD <= '0'; -- Input data
        wait for 10 ns;
        SHIFT_LOAD <= '1'; -- Shift data
        wait for 10 ns;
        D3 <= '0'; D2 <= '0'; D1 <= '1'; D0 <= '1'; SHIFT_LOAD <= '0'; -- Input new data
        wait for 10 ns;
        SHIFT_LOAD <= '1'; -- Shift data again
        wait;
    end process;
end Behavioral;

• 检查代码中可能存在的其他错误，确保代码编译通过。

参考代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity D_FF is
  port (
    D : in std_logic;
    CLK : in std_logic;
    Q : out std_logic
  );
end entity D_FF;
 
architecture D_FF_arch of D_FF is
begin
  process (CLK)
  begin
    if rising_edge(CLK) then
      Q <= D;
    end if;
  end process;
end architecture D_FF_arch;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity PISO is
    port (
        D0, D1, D2, D3 : in std_logic;
        SHIFT_LOAD : in std_logic;
        CLK : in std_logic;
        Q3 : out std_logic
    );
end entity PISO;
 
architecture behavioral of PISO is
    signal D_out : STD_LOGIC_VECTOR(3 downto 0);
    signal Q2 : STD_LOGIC;
begin
    DFF_3: entity work.D_FF port map (D3, CLK, D_out(3));
    DFF_2: entity work.D_FF port map (D2, CLK, D_out(2));
    DFF_1: entity work.D_FF port map (D1, CLK, D_out(1));
    DFF_0: entity work.D_FF port map (D0, CLK, D_out(0));
 
    Q2 <= D_out(2);
 
    process (CLK)
    begin
        if rising_edge(CLK) then
            if SHIFT_LOAD = '0' then
                D_out <= D3 & D2 & D1 & D0;
            else
                D_out <= '0' & D_out(3 downto 1);
            end if;
        end if;
    end process;
 
    Q3 <= D_out(3);
end behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity lab1_test is
end lab1_test;
 
architecture tb of lab1_test is
    signal D3, D2, D1, D0, SHIFT_LOAD, CLK : STD_LOGIC := '0';
    signal Q3 : STD_LOGIC;
    component PISO is
        Port ( D0, D1, D2, D3, SHIFT_LOAD, CLK : in STD_LOGIC; // 修改名称
               Q3 : out STD_LOGIC);
    end component;
begin
    dut: PISO
    port map (D0, D1, D2, D3, SHIFT_LOAD, CLK, Q3); // 修改连接
 
    CLK_process: process
    begin
        CLK <= not CLK after 5 ns;
    end process;
 
    stimulus: process
    begin
        wait for 10 ns;
        D3 <= '1'; D2 <= '0'; D1 <= '1'; D0 <= '0'; SHIFT_LOAD <= '0'; -- Input data
        wait for 10 ns;
        SHIFT_LOAD <= '1'; -- Shift data
        wait for 10 ns;
        D3 <= '0'; D2 <= '0'; D1 <= '1'; D0 <= '1'; SHIFT_LOAD <= '0'; -- Input new data
        wait for 10 ns;
        SHIFT_LOAD <= '1'; -- Shift data again
        wait;
    end process;
end Behavioral;