Jekaterina Viktorova

What’s Wire Bonding — How Chips Actually Connect to the World? In advanced packaging conversations, we often hear about 2.5D, 3D ICs, and chiplet integration. But behind the scenes, the most widely used interconnect method in chip packaging is still wire bonding. Here’s a breakdown of what’s happening in the image above: -> Wire Bonding Ultrathin gold or copper wires connect the bonding pads on the IC chip to the package’s interposer. These form the electrical path between the die and the outside world. -> Die and Mold Resin The silicon die (the “brains” of the chip) is encapsulated in mold resin for protection against moisture, dust, and mechanical damage. -> Pads and Solder Balls Pads on the die are the connection points for bonding wires, while solder balls create connections to the PCB or system board. -> Interposer A bridging layer that routes signals from the die to the package’s external pins or balls. Think of the die as a powerful workstation inside a sealed lab. Wire bonds are the power and data cables running through the walls—without them, the lab is isolated. -> Why It Matters Wire bonding remains the most common method in OSAT (Outsourced Semiconductor Assembly and Test) because it’s simple, reliable, and cost-effective. But as chips demand higher speeds and bandwidth, newer methods—like flip-chip, TSVs, and hybrid bonding—are stepping in for advanced performance. Key Takeaway: Wire bonding is the unsung hero of chip packaging—connecting silicon intelligence to the outside world for over 50 years. But as we move deeper into the era of 3D integration, the industry faces a balancing act: performance vs. manufacturability at scale. P.S. If you’re following semiconductor packaging, testing, and post-silicon trends, check out our blog The Semiconductor World. Link in comments. #Semiconductors #ChipPackaging #WireBonding #OSAT #AdvancedPackaging #ICDesign #PostSilicon #TestFlow #ATOMS

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UBM (Under Bump Metallization) Purpose: UBM is a critical layer in advanced semiconductor packaging, enabling reliable electrical and mechanical connections between the chip and solder bumps or copper pillars. Functions: Provides electrical interconnection, wetting for solder, diffusion barrier, and mechanical support. Prevents failures like delamination, solder voids, and electromigration. Applications: Used in Flip-Chip, Wafer-Level Packaging (WLP), Fan-Out WLP, 2.5D/3D IC stacking, and high-end 3D packaging (e.g., HBM, CoWoS). Materials: Multi-layer stacks: adhesion (Ti, TiW, Ta), seed/conductor (Cu), barrier (TiN, Ta, Ni), wetting (Au, Ag), and solder (Sn, SnAgCu). Etching: Selective etchants are used for each metal layer (e.g., HF+H₂O₂ for Ti, H₃PO₄+H₂O₂ for Cu, KI/I₂ for Au). Process control is crucial to avoid over-etching and ensure pad accuracy. Trends: Moving toward finer pitches (<50 μm), eco-friendly chemistries, cost reduction (less Au), and dry/plasma etching for better precision. Conclusion: UBM is foundational for next-gen semiconductor reliability, yield, and performance, especially as packaging becomes more complex and dense.

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The Fab Whisperer: The Most Misleading Metric in Fabs Every fab runs on metrics: OEE, cycle time, line yield, on-time delivery, cost per wafer/layer. But there’s one metric that, more often than not, misleads fabs into thinking they’re winning when in reality they’re falling behind: “Utilization”. Why it matters? On the surface, utilization feels like the right goal: keep tools busy, maximize output. But fabs are not simple factories — they’re complex, interconnected systems with bottlenecks and long cycle times. When fabs chase utilization too hard, it usually leads to: WIP bloats — tools run wafers just to look “busy,” flooding the downstream line with lots. Cycle time explosion — bottlenecks starve while non-bottlenecks overproduce. False sense of efficiency — high utilization ≠ high throughput. Technician overload — more setups, more firefighting. The paradox is that the harder a fab pushes utilization, the slower and more expensive it often gets. From the field: I once worked with a fab proudly reporting 95% utilization on bottleneck tools. Management celebrated. But wafer cycle times were climbing, and customers were missing deliveries. Tracing WIP revealed that the implant area was flooding the downstream Litho bottlenecks. Lots piled up in front of scanners, miss-managing critical recipes' priorities and inflating cycle time by weeks. Litho Utilization looked world-class. Actual fab delivery performance was collapsing. When we shifted the focus to throughput at the bottleneck and WIP turns at non-bottlenecks, cycle time improved 18% in just three months, and on-time delivery jumped from 70% to 93%. The fix: Stop chasing utilization as a headline fab metric. Focus on throughput at the bottleneck — the true limiter of output. Use metrics for bottleneck tools such as % Idle with WIP, throughput/tool/day or per shift. Focus on Dynamic Cycle Time (DCT) and WIP turns on non-bottlenecks — they reveal the hidden cost of overproduction. Align fab scheduling with pull principles wherever possible. Focus on FLOW. Teach fab leaders the difference between “busy” and “productive.” The most misleading metric isn’t the one you ignore. It’s the one you celebrate — while it quietly erodes flow. So… drop a comment if in your fab the focus on keeping tools busy trumps delivering wafers on time. What's your most misleading metric? #TheFabWhisperer #Semiconductor #FabOperations #Metrics #Utilization #CycleTime #ManufacturingExcellence

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Advanced Energy Unveils 401M Mid-Infrared Pyrometer for High-Precision Semiconductor Process Control Advanced Energy Industries (Nasdaq: AEIS) has introduced the 401M mid-infrared optical pyrometer, a next-generation solution for non-contact, high-precision temperature measurement in semiconductor and industrial environments. The product debuts this week at SEMICON West 2025 in Phoenix. Designed for speed and accuracy, the 401M delivers response times as low as 1 microsecond and temperature accuracy within ±3°C across a range of 50°C to 1,300°C. Its mid-infrared sensing technology allows for precise measurement through transparent materials—crucial for lamp-heated epitaxy, CVD, and thin-film coating processes where traditional near-IR pyrometers fall short. Integrated EtherCAT® communication simplifies tool integration, reducing external components and potential failure points. The system’s customizable wavelengths, working distances, and spot sizes enhance adaptability across advanced process environments, while backward compatibility with the OR400M platform ensures a cost-effective upgrade path. Advanced Energy’s launch underscores its focus on “Advancing the Angstrom Era”—pushing the limits of precision power and control technologies for next-generation semiconductor manufacturing. Thanks to Yahoo Finance for providing the full article with additional background, charts, and insights at the link below. 👇 https://lnkd.in/gNdNnRSY #ChipDesign,#SemiconductorManufacturing, #VLSI, #Lithography, #ICPackaging

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MAJOR ADVANCES IN (AI) TESTING DEMONSTRATED AT ECOC Exhibition 2025. I enjoyed a fascinating 3-way discussion about testing on the exhibition floor this week. Photonic integrated circuits operate at very high frequencies. We see InP and TFLN operating up to 110 GHz. Manufacturing is done at the wafer level, so we need to find partners who can test at such high frequencies, preferably automatically. In the video below, we discussed first with Lawrence van der Vegt, Head of Photonics at MPI Corporation. Founded in 1995 and headquartered in Hsinchu, Taiwan, MPI Corporation is a global technology leader in the testing of Semiconductors, Light Emitting Diodes, Photo Detectors, Lasers, Materials Research, and more. In September 2025, they announced the release of a fully integrated 250 GHz broadband test solution for the new Keysight Technologies NA5305A/7A PNA-X Frequency Extender. It builds on their deep expertise in sub-terahertz probing and on-wafer measurements. We explored why this is needed now. We also hear from Amir H. Ghadimi, CEO of Lightium based in Zurich, Switzerland. He explains what they need from an end-user perspective.  He also comments on a partnership between MPI Corporation and Axiomatic_AI. Design Engineer Mahdi Safari explains how their AI-driven SmartMeasure system utilises natural language to configure the probe station, select devices, and optimise the measurement order to maximise information retrieval. MPI tell me they have a lot of new developments on their roadmap to share at the OFC Conference 2026 and in Malaga next year. Onward to meet other Optica Corporate Members exhibiting this year and with a powerful deep-tech story to share! Does that apply to your company too? Join Optica and let's discuss.

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NVIDIA to Replace Silicon with Silicon Carbide (SiC) in CoWoS Interposer for Rubin Processors, Jukanlosreve reports at X. To me, this makes sense with the high thermal conductivity of SiC. And I heard rumors that the 12-inch SiC substrates from SICC CO. Ltd are targeted for this. https://lnkd.in/dzWYkKBx

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#DDR4 and #LPDDR4 Supply Tightens as #Shortages Drive Price Surge Rigid server orders are squeezing PC and consumer markets, pushing OEMs to accelerate DDR5 adoption. TrendForce reports consumer #electronics makers face soaring costs and material #shortages, while mobile #DRAM prices also climb. In 3Q25, LPDDR4X posted its steepest single-quarter rise in nearly a decade. With capacity tilted toward servers, most PC demand remains unmet. By July, 8GB DDR4 PC modules cost more than DDR5 equivalents in a rare price inversion. OEMs unable to secure #DDR4 have cut production and shifted to DDR5. DDR4 now faces high prices, low volume, and gradual phase-out. In data centres, DDR4 remains standard for #AI and high-efficiency workloads, prompting CSPs to issue intensive follow-up orders. Suppliers continue prioritising server contracts, though demand should ease as DDR5 gains ground in 2026. The consumer DRAM market—covering TVs, networking, controllers, and industrial uses—faces the harshest #shortages since it ranks last in allocation. Prices surged 60–85% in July, with 3Q25 contract prices revised up by 85–90%. For LPDDR4X, used in mainstream and entry-level phones, supply fears have grown as US and Korean firms plan output cuts from 2025–26. Panic buying and bidding wars lifted TrendForce’s 3Q25 forecast to a 38–43% increase. Meanwhile, LPDDR5X supply is healthier thanks to process migration. Adoption has expanded to mid/high-end phones, notebooks, and AI servers. With average prices lower than other DRAM, suppliers plan moderate hikes, with 3Q25 contracts rising 10–15% QoQ. https://lnkd.in/eUd3zDj8 Personal addition 🤓: The DDR4 shortage is still going on. The big ones are going out and the market gets flooded with big last time buys to stock up goods. Legacy DDR4 suppliers will be overrun by new demands and need to set priority lists for customers. Of course, we already have solutions for the long run. Get in contact with us ([email protected]), if you search longterm available solutions. Until that, the madness goes on. #embedded #embeddedsystems #IIOT #industry40 #SSD #storage #memory #electronics #DRAM #NAND #flashmemory #semiconductor altec ComputerSysteme GmbH #technology

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