Verilog练习：HDLBits笔记5

二、Verilog Language

Procedures

1、Always blocks(Combinational)

Problem Statement：

Build an AND gate using both an assign statement and a combinational always block. 

module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
    assign out_assign = a & b;
    
    always@(*)begin
        out_alwaysblock = a & b;
    end

endmodule

2、Always blocks(clocked)

Problem Statement：

Build an XOR gate three ways, using an assign statement, a combinational always block, and a clocked always block. Note that the clocked always block produces a different circuit from the other two: There is a flip-flop so the output is delayed.

module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   
);
    assign out_assign = a ^ b;
    
    always@(*) begin
        out_always_comb = a ^ b;
    end
    
    always@(posedge clk) begin
        out_always_ff = a ^ b;
    end
        

endmodule

 3、If statement

Problem Statement：

Build a 2-to-1 mux that chooses between a and b. Choose b if both sel_b1 and sel_b2 are true. Otherwise, choose a. Do the same twice, once using assign statements and once using a procedural if statement.

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sel_b1	sel_b2	out_assign out_always