【HDLBits习题详解 4】Verification: Writing Testbenches

1. Tb/clock（Clock）

module top_module ();
    // input
	reg clk;
    
    // ---------- Initial ----------
    initial clk = 0;
    
    always #5 clk = ~clk;
    
    // ---------- Instantiation ----------
    dut uut ( 
        .clk	(clk)
    );
endmodule

2. Tb/tb1（Testbench1）

module top_module ( 
    output reg A, 
    output reg B
);
    // ---------- Initial ----------
    initial begin
		A = 0;
        B = 0;
        
        #10 A = 1;
        #5	B = 1;
        #5	A = 0;
        #20 B = 0;
    end
endmodule

3. Tb/and（AND gate）

module top_module();
    // output
    wire			out;
    // input
    reg		[1:0]	in;
    
    // ---------- Initial ----------
    initial begin
        in = 2'd0;
        
        #10	in[0] 	= 1;
        #10	in		= 2'b10;
        #10	in[0]	= 1;
    end
    
    // ---------- Instantiation ----------
    andgate uut (
        .out	(out),
        .in		(in)
    );
endmodule

4. Tb/tb2（Testbench2）

module top_module();
	// output
    wire			out;
    // input
    reg				clk;
    reg				in;
    reg		[2:0]	s;
    
    // ---------- Initial ----------
    // 输入值clk
    initial 	clk = 0;
    always 	#5 	clk = ~clk;
    
    // 输入值in
    initial begin
        in = 0;
        
        #20	in = 1;
        #10	in = 0;
        #10	in = 1;
        #30	in = 0;
    end
    
    // 输入值s
    initial begin
    	s = 3'd2;
        
        #10	s = 3'd6;
        #10	s = 3'd2;
        #10	s = 3'd7;
        #10	s = 3'd0;
    end
    
    // ---------- Instantiaion ----------
    q7 uut (
        .out	(out),
        .clk	(clk),
        .in		(in),
        .s		(s)
    );
endmodule

5. Tb/tff（T flip-flop）

module top_module ();
	// output
    wire	q;
    // input
    reg		clk;
    reg		reset;
    reg		t;
    
    // Initial
    // 输入值clk
    initial 	clk = 0;
    always 	#5 	clk = ~clk;
    
    // 输入值reset
    initial begin
        reset = 0;
        
        #10	reset = 1;
        #20	reset = 0;
    end
    
    // 输入值t
    initial	begin
        t = 0;
        
        #40	t = 1;
    end
    
    // Instantiation
    tff uut (
        .q		(q),
        .clk	(clk),
        .reset	(reset),
        .t		(t)
    );
endmodule