【HDLBits习题详解 5】CS450（更新中......）

1. Cs450/timer

module top_module (
    output 	reg			tc,
	input 				clk, 
	input 				load, 
	input 		[9:0] 	data
);
    reg [9:0] counter;
    
    always @(posedge clk) begin
        if (load == 1'b1) begin
            if (data == 10'd0) begin
                tc <= 1'b1;
            end else begin
            	tc <= 1'b0;
            end
        end else if (counter == 10'd1) begin
            tc <= 1'b1;
        end else begin
            tc <= tc;
        end
    end
    
    always @(posedge clk) begin
        if (load == 1'b1) begin
            counter <= data;
        end else if (counter == 10'd0) begin
            counter <= counter;
        end else begin
            counter <= counter + 10'h3ff;
        end
    end
endmodule

2. Cs450/counter 2bc

module top_module
#(
	parameter SNT	= 0,
    parameter WNT	= 1,
    parameter WT	= 2,
    parameter ST	= 3
)
(
    output 	[1:0] 	state,
    input 			clk,
    input 			areset,
    input 			train_valid,
    input 			train_taken
);
    reg [1:0] sta;
    reg [1:0] nex_sta;
    
    // 状态值更新
    always @(posedge clk, posedge areset) begin
        if (areset == 1'b1) begin
            sta <= ;
        end else begin
            sta <= nex_sta;
        end
    end
    
    // 状态转移表
    always @(*) begin
        case (sta)
            
        endcase
    end
    
    // 输出赋值
    
endmodule