【HDLbits Serial--快速入门Verilog Program】

本系列介绍HDLBits刷题快速入门，在上学期间学习可编程逻辑器件这门课时，老师曾建议我们刷过这个网站；希望能帮助刚入门Verilog的读者快速了解语法；
本篇文章主要介绍Verilog中的wire类型和assign赋值语句；
刚兴趣的读者可以了解一下；
HDLbits网站：https://hdlbits.01xz.net/wiki/Main_Page

0 前言

	--support the verilog-2001;
	--1.Design a circuit require several steps: Write HDL code; compile the code to produce a circuit; simulate the circuite and fix the bugs;
		--1.write code: 
		--2.Compile and produce a circuite circuit.
		--3.Simulation: compiled circuit is simulated to test whether it functions correctly.
		--4.compare : compare your compiled circuit and reference circuit; Besides compare the timing diagrams with reference timing diagrams;
	**The top module name and port names must not be changed**
	
	Example: 
		Build a circuit with no inputs and one output that outputs a constant 0;
	```v
	module top_module(
		Output zero
	);
		Assign zero = 1'b0;
	
	endmodule
	```