FSM next-state logic

FSM7-自动售货机2 BUAA

verilog按键消抖模块module debounce_fsm ( input clk, // 主时钟 input rst_n, // 复位信号，低电平有效 input key_in, // 原始按键输入 output reg key_out // 消抖后的按键输出 ); //------------------------------------- // 参数定义 //------------------------------------- parameter CNT_MAX = 20_000_000; // 假设系统时钟为 100MHz，对应约 200ms 抖动时间 //------------------------------------- // 状态类型定义 //------------------------------------- typedef enum logic [1:0] { IDLE, PRESS_CHK, RELEASE_CHK } state_t; state_t current_state, next_state; //------------------------------------- // 计数器定义 //------------------------------------- reg [31:0] cnt; //------------------------------------- // 状态寄存器更新 //------------------------------------- always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) current_state <= IDLE; else current_state <= next_state; end //------------------------------------- // 状态转移逻辑 //------------------------------------- always_comb begin next_state = current_state; case (current_state) IDLE: begin if (!key_in) next_state = PRESS_CHK; end PRESS_CHK: begin if (cnt == CNT_MAX) next_state = IDLE; end RELEASE_CHK: begin if (cnt == CNT_MAX) next_state = IDLE; end default: next_state = IDLE; endcase end //------------------------------------- // 计时器与标志信号逻辑 //------------------------------------- always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin cnt <= 0; key_out <= 1'b1; end else begin case (current_state) IDLE: begin cnt <= 0; if (!key_in) key_out <= 1'b0; // 按键按下 end PRESS_CHK: begin if (cnt < CNT_MAX) cnt <= cnt + 1; else begin key_out <= 1'b0; // 确认按下 end end RELEASE_CHK: begin if (cnt < CNT_MAX) cnt <= cnt + 1; else begin key_out <= 1'b1; // 确认释放 end end endcase end end endmodule 生成测试代码

module fsm_controller ( input wire clk, input wire reset, input wire start_signal, output reg done_signal ); parameter IDLE = 2'b00; parameter PROCESSING = 2'b01; parameter COMPLETING = 2'b10; parameter ERROR = 2'b11; reg [1:0] current_state, next_state; always @(posedge clk or posedge reset) begin if (reset) begin current_state <= IDLE; end else begin current_state <= next_state; end end always @(*) begin case (current_state) IDLE : begin if (start_signal) begin next_state = PROCESSING; end else begin next_state = IDLE; end end PROCESSING : begin next_state = COMPLETING; end COMPLETING : begin next_state = IDLE; end ERROR : begin next_state = IDLE; end default : next_state = IDLE; endcase end always @(posedge clk) begin if (reset) begin done_signal <= 0; end else begin case (next_state) COMPLETING : done_signal <= 1; default : done_signal <= 0; endcase end end endmodule基于此代码，为我设计一个功能更加复杂的代码，以及测试平台代码