adrv9009配置245.76MHZ时钟

最新推荐文章于 2025-05-27 09:15:03 发布
最新推荐文章于 2025-05-27 09:15:03 发布
阅读量1.9k 收藏 17
点赞数 6
CC 4.0 BY-SA版权
文章标签： fpga开发 射频工程 嵌入式硬件
版权声明：本文为博主原创文章，遵循 CC 4.0 BY-SA 版权协议，转载请附上原文出处链接和本声明。
本文链接：https://blog.csdn.net/qq_48328745/article/details/142101772

        今天需要验证高带宽的射频收发，需要将9009配置为245.76MHZ的时钟。捣鼓半天根据9009官方配置代码修改完成，下面记录一下如何更改。

        1.官方给定的SDK示例代码默认配置122.88MHZ ，这个主要是通过 talise_config.c中的结构体talInit 所确定的。为了便于调整我们直接修改相关参数，再构造一个结构体245.76MHZ的talInit2

taliseInit_t talInit2 = {
	/* SPI settings */
	.spiSettings =
	{
		.MSBFirst            = 1,  /* 1 = MSBFirst, 0 = LSBFirst */
		.enSpiStreaming      = 0,  /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
		.autoIncAddrUp       = 1,  /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
		.fourWireMode        = 1,  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
		.cmosPadDrvStrength  = TAL_CMOSPAD_DRV_2X /* Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */
	},

	/* Rx settings */
	.rx =
	{
		.rxProfile =
		{
			.rxFir =
			{
				.gain_dB = -6,                /* filter gain */
				.numFirCoefs = 48,            /* number of coefficients in the FIR filter */
				.coefs = &rxFirCoefs2[0]
			},
			.rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
			.rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
			.rhb1Decimation = 2,            /* RX Half band 1 decimation (1 or 2) */
			.rxOutputRate_kHz = 122880,            /* Rx IQ data rate in kHz */
			.rfBandwidth_Hz = 100000000,    /* The Rx RF passband bandwidth for the profile */
			.rxBbf3dBCorner_kHz = 100000,    /* Rx BBF 3dB corner in kHz */
			.rxAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},            /* pointer to custom ADC profile */
			.rxDdcMode = TAL_RXDDC_BYPASS,   /* Rx DDC mode */
			.rxNcoShifterCfg =
			{
				.bandAInputBandWidth_kHz = 0,
				.bandAInputCenterFreq_kHz = 0,
				.bandANco1Freq_kHz = 0,
				.bandANco2Freq_kHz = 0,
				.bandBInputBandWidth_kHz = 0,
				.bandBInputCenterFreq_kHz = 0,
				.bandBNco1Freq_kHz = 0,
				.bandBNco2Freq_kHz = 0
			}
		},
		.framerSel = TAL_FRAMER_A,            /* Rx JESD204b framer configuration */
		.rxGainCtrl =
		{
			.gainMode = TAL_MGC,            /* taliserxGainMode_t gainMode */
			.rx1GainIndex = 255,            /* uint8_t rx1GainIndex */
			.rx2GainIndex = 255,            /* uint8_t rx2GainIndex */
			.rx1MaxGainIndex = 255,            /* uint8_t rx1MaxGainIndex */
			.rx1MinGainIndex = 195,            /* uint8_t rx1MinGainIndex */
			.rx2MaxGainIndex = 255,            /* uint8_t rx2MaxGainIndex */
			.rx2MinGainIndex = 195            /* uint8_t rx2MinGainIndex */
		},
		.rxChannels = TAL_RX1RX2,                /* The desired Rx Channels to enable during initialization */
	},


	/* Tx settings */
	.tx =
	{
		.txProfile =
		{
			.dacDiv = 1,                        /* The divider used to generate the DAC clock */
			.txFir =
			{
				.gain_dB = 6,                        /* filter gain */
				.numFirCoefs = 80,                    /* number of coefficients in the FIR filter */
				.coefs = &txFirCoefs2[0]
			},
			.txFirInterpolation = 2,                    /* The Tx digital FIR filter interpolation (1,2,4) */
			.thb1Interpolation = 2,                    /* Tx Halfband1 filter interpolation (1,2) */
			.thb2Interpolation = 2,                    /* Tx Halfband2 filter interpolation (1,2)*/
			.thb3Interpolation = 2,                    /* Tx Halfband3 filter interpolation (1,2)*/
			.txInt5Interpolation = 1,                    /* Tx Int5 filter interpolation (1,5) */
			.txInputRate_kHz = 122880,                    /* Primary Signal BW */
			.primarySigBandwidth_Hz = 50000000,    /* The Rx RF passband bandwidth for the profile */
			.rfBandwidth_Hz = 100000000,            /* The Tx RF passband bandwidth for the profile */
			.txDac3dBCorner_kHz = 187000,                /* The DAC filter 3dB corner in kHz */
			.txBbf3dBCorner_kHz = 56000,                /* The BBF 3dB corner in kHz */
			.loopBackAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905}
		},
		.deframerSel = TAL_DEFRAMER_A,                    /* Talise JESD204b deframer config for the Tx data path */
		.txChannels = TAL_TX1TX2,                            /* The desired Tx channels to enable during initialization */
		.txAttenStepSize = TAL_TXATTEN_0P05_DB,            /* Tx Attenuation step size */
		.tx1Atten_mdB = 0,                            /* Initial Tx1 Attenuation */
		.tx2Atten_mdB = 0,                            /* Initial Tx2 Attenuation */
		.disTxDataIfPllUnlock = TAL_TXDIS_TX_RAMP_DOWN_TO_ZERO    /* Options to disable the transmit data when the RFPLL unlocks. */
	},


	/* ObsRx settings */
	.obsRx =
	{
		.orxProfile =
		{
			.rxFir =
			{
				.gain_dB = -6,                /* filter gain */
				.numFirCoefs = 48,            /* number of coefficients in the FIR filter */
				.coefs = &obsrxFirCoefs2[0]
			},
			.rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
			.rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
			.rhb1Decimation = 2,            /* RX Half band 1 decimation (1 or 2) */
			.orxOutputRate_kHz = 122880,            /* Rx IQ data rate in kHz */
			.rfBandwidth_Hz = 100000000,    /* The Rx RF passband bandwidth for the profile */
			.rxBbf3dBCorner_kHz = 225000,    /* Rx BBF 3dB corner in kHz */
			.orxLowPassAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},
			.orxBandPassAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},
			.orxDdcMode = TAL_ORXDDC_DISABLED,   /* ORx DDC mode */
			.orxMergeFilter  = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
		},
		.orxGainCtrl =
		{
			.gainMode = TAL_MGC,
			.orx1GainIndex = 255,
			.orx2GainIndex = 255,
			.orx1MaxGainIndex = 255,
			.orx1MinGainIndex = 195,
			.orx2MaxGainIndex = 255,
			.orx2MinGainIndex = 195
		},
		.framerSel = TAL_FRAMER_B,                /* ObsRx JESD204b framer configuration */
		.obsRxChannelsEnable = TAL_ORX1ORX2,        /* The desired ObsRx Channels to enable during initialization */
		.obsRxLoSource = TAL_OBSLO_RF_PLL                /* The ORx mixers can use the TX_PLL */
	},

	/* Digital Clock Settings */
	.clocks =
	{
		.deviceClock_kHz = 245760,            /* CLKPLL and device reference clock frequency in kHz */
		.clkPllVcoFreq_kHz = 9830400,        /* CLKPLL VCO frequency in kHz */
		.clkPllHsDiv = TAL_HSDIV_2P5,            /* CLKPLL high speed clock divider */
		.rfPllUseExternalLo = 0,                /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */
		.rfPllPhaseSyncMode = TAL_RFPLLMCS_NOSYNC                /* RFPLL MCS (Phase sync) mode */
	},

	/* JESD204B settings */
	.jesd204Settings =
	{
		/* Framer A settings */
		.framerA =
		{
			.bankId = 1,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
			.M = 4,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
			.K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
			.F = 4,                            /* F (number of bytes per frame) */
			.Np = 16,                            /* Np (converter sample resolution) */
			.scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
			.externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
			.serializerLanesEnabled = 0x03,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
			.serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
			.lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbInSelect = 0,                /* syncbInSelect; */
			.overSample = 0,                    /* 1=overSample, 0=bitRepeat */
			.syncbInLvdsMode = 1,
			.syncbInLvdsPnInvert = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		/* Framer B settings */
		.framerB =
		{
			.bankId = 0,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
			.M = 2,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
			.K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
			.F = 2,                            /* F (number of bytes per frame) */
			.Np = 16,                            /* Np (converter sample resolution) */
			.scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
			.externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
			.serializerLanesEnabled = 0x0C,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
			.serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
			.lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbInSelect = 1,                /* syncbInSelect; */
			.overSample = 0,                    /* 1=overSample, 0=bitRepeat */
			.syncbInLvdsMode = 1,
			.syncbInLvdsPnInvert = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		/* Deframer A settings */
		.deframerA =
		{
			.bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
			.M = 4,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
			.K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
			.scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
			.externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
			.deserializerLanesEnabled = 0x0F,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
			.deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
			.lmfcOffset = 17,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbOutSelect = 0,                /* SYNCBOUT0/1 select */
			.Np = 16,                /* Np (converter sample resolution) */
			.syncbOutLvdsMode = 1,
			.syncbOutLvdsPnInvert = 0,
			.syncbOutCmosSlewRate = 0,
			.syncbOutCmosDriveLevel = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		/* Deframer B settings */
		.deframerB =
		{
			.bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
			.M = 0,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
			.K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
			.scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
			.externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
			.deserializerLanesEnabled = 0x00,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
			.deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
			.lmfcOffset = 0,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbOutSelect = 1,                /* SYNCBOUT0/1 select */
			.Np = 16,                /* Np (converter sample resolution) */
			.syncbOutLvdsMode = 1,
			.syncbOutLvdsPnInvert = 0,
			.syncbOutCmosSlewRate = 0,
			.syncbOutCmosDriveLevel = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		.serAmplitude = 15,                    /* Serializer amplitude setting. Default = 15. Range is 0..15 */
		.serPreEmphasis = 1,                /* Serializer pre-emphasis setting. Default = 1 Range is 0..4 */
		.serInvertLanePolarity = 0,            /* Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */
		.desInvertLanePolarity = 0,            /* Deserializer Lane PN inversion select.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */
		.desEqSetting = 1,                    /* Deserializer Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */
		.sysrefLvdsMode = 1,                /* Use LVDS inputs on Talise for SYSREF */
		.sysrefLvdsPnInvert = 0              /*0= Do not PN invert SYSREF */
	}
};
//Only needs to be called if user wants to setup AGC parameters
static taliseAgcCfg_t rxAgcCtrl = {
	4,
	255,
	195,
	255,
	195,
	30720,  /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 245.76 Mhz) */
	10,
	10,
	16,
	0,
	1,
	0,
	0,
	0,
	1,
	31,
	246,
	4,
	1,          /*!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
	/* agcPower */
	{
		1,      /*!<1-bit field, enables the Rx power measurement block. */
		1,      /*!<1-bit field, allows using Rx PFIR for power measurement. */
		0,      /*!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */
		9,      /*!<AGC power measurement detect lower 0 threshold. Default = -12dBFS == 5, 7-bit register value where max = 0x7F, min = 0x00 */
		2,      /*!<AGC power measurement detect lower 1 threshold. Default = (offset) 4dB == 0, 4-bit register value where  max = 0xF, min = 0x00 */
		4,      /*!<AGC power measurement detect lower 0 recovery gain step. Default = 2dB - based on gain table step  size, 5-bit register value where max = 0x1F, min = 0x00 */
		4,      /*!<AGC power measurement detect lower 1 recovery gain step. Default = 4dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
		5,      /*!< power measurement duration used by the decimated power block. Default = 0x05, 5-bit register value where max = 0x1F, min = 0x00 */
		5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		2,      /*!<Default value should be 2*/
		0,
		0
	},
	/* agcPeak */
	{
		205,        /*!<1st update interval for the multiple time constant in AGC loop mode, Default:205. */
		2,          /*!<sets the 2nd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of  agcUnderRangeLowInterval??, Default: 4 */
		4,          /*!<sets the 3rd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeMidInterval and agcUnderRangeLowInterval, Default: 4 */
		39,         /*!<AGC APD high threshold. Default=0x1F, 6-bit register value where max=0x3F, min =0x00 */
		49,         /*!<AGC APD peak detect high threshold. default = 0x1F, 6-bit register value where max = 0x3F, min = 0x00.  Set to 3dB below apdHighThresh */
		23,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max =0x3F, min = 0x00 */
		19,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max = 0x3F, min = 0x00 . Set to 3dB below apdLowThresh  */
		6,          /*!<AGC APD peak detect upper threshold count. Default = 0x06 8-bit register value where max = 0xFF, min = 0x20  */
		3,          /*!<AGC APD peak detect lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00? */
		4,          /*!<AGC APD peak detect attack gain step. Default = 2dB step - based on gain table step size, 5-bit register  value, where max = 0x1F, min = 0x00  */
		2,          /*!<AGC APD gain index step size. Recommended to be same as hb2GainStepRecovery. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00  */
		1,          /*!<1-bit field, enables or disables the HB2 overload detector.  */
		1,          /*!<3-bit field. Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. */
		1,          /*!<4-bit field. Sets the number of actual overloads required to trigger the overload signal.  */
		181,        /*!<AGC decimator output high threshold. Default = 0xB5, 8-bit register value where max = 0xFF, min = 0x00 */
		45,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
		90,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
		128,        /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
		6,          /*!<AGC HB2 output upper threshold count. Default = 0x06, 8-bit register value where max = 0xFF, min =  0x20 */
		3,          /*!<AGC HB2 output lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
		2,          /*!<AGC decimator gain index step size. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
		4,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 0 triggers a programmable number  of times. Default = 0x08, 5-bit register value where max = 0x1F, min = 0x00 */
		8,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 1 triggers a programmable number of times. Default = 0x04, 5-bit register value where max = 0x1F, min = 0x00 */
		4,          /*!<AGC decimator output attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
		1,
		0,
		0
	}
};

以及在这个配置文件的开头增加相关245MHZ滤波器参数

int16_t txFirCoefs[20] = {33, -77, 123, -158, 171, -112, -155, 1040, -3011, 20121, -3011, 1040, -155, -112, 171, -158, 123, -77, 33, 0};

int16_t rxFirCoefs[48] = {-7, -23, 33, 50, -70, -110, 144, 205, -259, -356, 437, 581, -698, -916, 1082, 1415, -1655, -2209, 2567, 3615, -4351, -7169, 9329, 31129, 31129, 9329, -7169, -4351, 3615, 2567, -2209, -1655, 1415, 1082, -916, -698, 581, 437, -356, -259, 205, 144, -110, -70, 50,  33, -23, -7};

int16_t obsrxFirCoefs[48] = {-7, -21, 31, 48, -67, -106, 124, 164, -275, -334, 440, 552, -694, -872, 1069, 1351, -1633, -2111, 2541, 3477, -4295, -6877, 9433, 30825, 30825, 9433, -6877, -4295, 3477, 2541, -2111, -1633, 1351, 1069, -872, -694, 552, 440, -334, -275, 164, 124, -106, -67, 48, 31, -21, 7};

然后在talise_config.h文件中，增加一个外部引用结构体说明

/**
 * \file adrv9009/profiles/tx_bw100_ir122p88_rx_bw100_or122p88_orx_bw100_or122p88_dc122p88/talise_config.h
 * \brief Talise configuration external declarations
 *
 * \brief Contains structure definitions for tal_config.c
 *
 * Copyright 2015-2017 Analog Devices Inc.
 * Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
 *
 * The top level structure taliseDevice_t talDevice uses keyword
 * extern to allow the application layer main() to have visibility
 * to these settings.
 */

#ifndef TAL_INIT_H_
#define TAL_INIT_H_

#ifdef __cplusplus
extern "C" {
#endif

extern taliseDevice_t talDevice;
extern taliseInit_t talInit;
extern taliseInit_t talInit2;

#ifdef __cplusplus
}
#endif

#endif

然后在app_transceiver.c传输配置函数修改倍频器类型

	struct adxcvr_init rx_adxcvr_init = {
		"rx_adxcvr",
		RX_XCVR_BASEADDR,
		0,
		3,
		0,
		1,
		rx_lane_rate_khz,
		device_clock,
	};

//以下为这个配置结构体的相关变量
struct adxcvr_init {
	const char *name;
	uint32_t base;
	uint32_t sys_clk_sel;
	uint32_t out_clk_sel;
	bool cpll_enable;
	bool lpm_enable;
	uint32_t lane_rate_khz;
	uint32_t ref_rate_khz;
};
//

因为这个是高速收发速率所以CPLL就不适用我们得使用QPLL来进行倍频，下图为配置的底层源码，所以修改为0就可以使用QPLL跑

	if (xcvr->cpll_enable)
		ret = xilinx_xcvr_calc_cpll_config(&xcvr->xlx_xcvr, parent_rate, rate,
						   &cpll_conf, &out_div);
	else
		ret = xilinx_xcvr_calc_qpll_config(&xcvr->xlx_xcvr, parent_rate, rate,
						   &qpll_conf, &out_div);

最后在主函数headless.c中main修改一下配置的结构体就行，将talInit改成talInit2就行

最后成功配置为254.76MHZ的收发速率。

基于FPGA ZC706的AD9371&ADRV9009网口驱动配置
weixin_46679868的博客
04-28 3476
在本设计中，通过配置ZC706的LWIP模块实现网口通信，网口主要用来控制9371和9009的参数及配置。在本系统中，采用ZC706+FreeRTOS的配置模式，实现高速网口通信。 1. LWIP配置过程简介 如下图所示，在Project中选择“LWIP Echo Server”选项进行工程建立 2. 工程建立完成后，配置LWIP的工作参数，实现高速通信 在配置完成LWIP后，需要修改一些默认参...
ADRV9009的学习历程（一）
weixin_42868560的博客
08-11 1万+
** AD9361的同胞ADRV9009 ** 终于记录一下了 距离第一次想写博客记录自己学习的点点滴滴，大概已经过去有一年有余。一直都是停留在心有余而力不足的境界。 基本每次做项目遇到问题都会来CSDN寻求帮助，这里虽离庙堂较远，但高手云集。每每读来，思绪万千，次次膜拜。 趁这次又学习了一样新物件，就记录一下，望大神看见能赐教一下。 ADRV9009 最近有项目要用到ADRV9009这个芯片。就来学习一下。做过AD9361的都知道，ADI官方会给出这个芯片的参考手册、数据手册和驱动程序。当然我只是见过AD
ADRV9026 JESD204B测试
RFSOC的博客
05-27 311
ADRV9026是一款高性能射频收发器，专为5G基站和MIMO系统设计。该器件集成四个收发通道、两个观测接收器及五个PLL，支持JESD204B接口。其直接变频架构配合数字校准功能，可提供宽动态范围、低噪声性能，同时降低基带处理负担。适用于宏基站、小基站等蜂窝基础设施，实现高效率的射频信号处理与转换。
FPGA、AD9371、AD9009、RF SOC介绍
weixin_46679868的博客
04-26 7850
随着5G的快速发展和物联网的到来，无线通信这一块这些年有了充分的发展和进步，站上投资的风口期和快速布局发展期，为跟进5G的步伐，我们制作了一系列技术硬件设计来适应时代的发展，包括但不限于以下几个方向，现介绍如下： FPGA介绍 FPGA发展很快，但大部分FPGA核心技术都 掌握在国外公司的手中。芯片设计，光刻机，操作系统设计都只有国外引领潮流，我们跟随潮流。国内FPGA发展相对缓慢，现市场上主要...
ADRV9009文档
02-25
ADRV9009芯片资料 文档 The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.
ADRV9008-x-ADRV9009-profile-config-tool.rar
08-26
ADRV9008-x-ADRV9009 配置工具下载，滤波器设置，可视化配置，快速配置9008 9009
ADRV9009配置文件（验证可用）.zip
09-15
ADRV9009配置文件（验证可用）.zip
ADRV9009-W-PCBZ-Schematic-RevB.pdf
06-12
adrv9009芯片参考设计原理图，adrv9009参考demo板的设计范例， ad9009 射频前端设计范例；
ADRV9009 项目系统架构——手册介绍
热门推荐
Bronceyang的博客
11-03 1万+
一、9009介绍 ADRV9009 是一款双通道 RF 发送器和接收器，带有一个观察接收器。 工作频率范围为 75 MHz 至 6 GHz 。该器件在其发射器上支持高达 450 MHz 的合成带宽。该设备的接收器部分既可以作为支持高达 200 MHz 带宽的双通道接收器运行，也可以作为支持高达 450 MHz 带宽的单通道观测接收器运行。接收器部分在时分双工 (TDD) 操作中在单通道和双通道模式之间切换，在接收器时隙期间使用双通道接收器模式，在收发器时隙中使用单通道观测接收器。单通道观测接收器可以选择
ADRV9009-SDCARD.zip
08-16
在ADRV9009的应用中，ZC706可以作为数据处理和控制的核心，实现对ADRV9009的配置、采样率设置、滤波器设计等功能。 使用这个压缩包中的资源，开发者可以学习如何配置和控制ADRV9009，了解其工作原理，并结合ZC706...
zc706_adrv9009.rar
08-04
通过SDK，开发者可以实现对ADRV9009的配置、数据读取以及进一步的数据处理算法。 在实际应用中，这样的工程可以帮助用户快速搭建一个原型系统，进行信号捕获、分析和处理。对于研究者和工程师来说，它提供了深入...
ADRV9008-x-ADRV9009-profile-config-tool-filter-wizard-v2.4.zip
08-16
在官网下载的文档，有需要的还是去官网下载，那里面更全，更权威，而且是免费的！在这只是想保存一下资源。
ADI RFIC ADRV9009 datasheet
01-03
ADI RFIC ADRV9009 datasheet
ADRV9009配置工具，生成滤波器系数，生成talise_config.c文件等
08-31
该文件通常包括了对ADRV9009内部模块的配置，如ADC和DAC采样率设置、数字预失真（DPD）参数、IQ校正、时钟管理等。 ADI公司作为全球知名的半导体供应商，提供了丰富的技术支持。用户不仅可以免费下载ADRV9009的配置...
adrv9009_fmcomms8_sync_test_bash_ad_rf_adrv9009_测试脚本.zip
10-11
3. **同步测试**：测试ADRV9009的时钟同步和数据同步功能，这对于多标准无线通信至关重要，确保信号在接收和发送过程中保持一致。 4. **信号生成与分析**：通过生成特定的测试信号，然后使用示波器或频谱分析仪等...
ADRV9009 8R8T 同步系统
weixin_29905597的博客
07-19 2212
1.FPGA处理器使用的是：XCZU9EG-2FFVB1156I，接口支持网卡，串口，预留的有光口，485，LVDS; 收发器：使用的ADRV9009 8 Rx 8Tx; 2.硬件主板 3.ADRV9009板 4.同步精度小于1度
搭建ADRV9009_ZCU102工程的SDR平台
zhong_kai的博客
07-20 8000
搭建ADRV9009_ZCU102工程的SDR平台ADRV9009介绍搭建例程 ADRV9009介绍 ADRV9009是一款高集成度射频(RF)、捷变收发器，提供双通道发射器和接收器、集成式频率合成器以及数字信号处理功能。这款IC具备多样化的高性能和低功耗组合，以满足3G、4G和5G宏蜂窝时分双工(TDD)基站应用要求。 接收路径由两个独立的宽带宽、直接变频接收器组成，具有一流的动态范围。该...
ADRV9009配置参数验证
weixin_42905573的博客
01-17 3448
函数原型： TALISE_verifyProfiles(); //入口函数，其中调用下面三个子函数 talVerifyRxProfile(); //Rx通道的参数验证 talVerifyOrxProfile(); //Orx的参数验证 talVerifyTxProfile(); //Tx 的参数验证 1，TX 的参数验证具体如下（ talVerifyTxProfile() ） txInputRate_kHz：Tx 端的数据速率，KHz 为单位。参数限制： 15000 &
adrv9009配置245
最新发布
06-25
配置ADRV9009设备的245接口（通常指USB 2.45接口，也即 Cypress CY7C68013A USB 2.0 控制器）涉及多个步骤，包括硬件连接、固件加载以及软件配置。以下是一个详细的指南： ### 硬件连接 确保ADRV9009与FPGA或主控...
评论 2
添加红包

请填写红包祝福语或标题

个

红包个数最小为10个

元

红包金额最低5元

当前余额3.43元 前往充值 >
需支付：10.00元
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付元
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明：

1.余额是钱包充值的虚拟货币，按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载，可以购买VIP、付费专栏及课程。

余额充值