国产DSP FT-M6678开发-DDR初始化流程及正确log展示

文章详细记录了对DDR3区域的内存测试过程,包括PHY级硬/软延时、状态观察、GTLLVL、RDDLVL以及走位测试(BIST),展示了64bit数据填充、地址测试和位线测试的结果。

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[C66xx_0] phy_wrlvl_hard0_delay_X

PHY_47, value = 0x104

PHY_111, value = 0x104

PHY_175, value = 0xd8

PHY_239, value = 0xe4

PHY_303, value = 0x90

PHY_367, value = 0xa8

PHY_431, value = 0x60

PHY_495, value = 0x6c

PHY_559, value = 0xcc

phy_wrlvl_hard1_delay_X

PHY_47, value = 0x110

PHY_111, value = 0x110

PHY_175, value = 0xf0

PHY_239, value = 0xfc

PHY_303, value = 0xa8

PHY_367, value = 0xb4

PHY_431, value = 0x6c

PHY_495, value = 0x78

PHY_559, value = 0xe4

phy_wrlvl_status_obs_X

PHY_48, value = 0xb00

PHY_112, value = 0xb00

PHY_176, value = 0xb00

PHY_240, value = 0xb00

PHY_304, value = 0xb00

PHY_368, value = 0xb00

PHY_432, value = 0xb00

PHY_496, value = 0xb00

PHY_560, value = 0xb00

phy_wrlvl_clk_wrdqs_slave_delay_X

PHY_4, value = 0x10a

PHY_68, value = 0x10a

PHY_132, value = 0xe4

PHY_196, value = 0xf0

PHY_260, value = 0x9c

PHY_324, value = 0xae

PHY_388, value = 0x66

PHY_452, value = 0x72

PHY_516, value = 0xd8

wrlvl finished

phy_gtlvl_hard0_delay_X

PHY_50, value = 0x3cc

PHY_114, value = 0x3cc

PHY_178, value = 0x39c

PHY_242, value = 0x3a8

PHY_306, value = 0x348

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