锁机制 -（1）ARM64内存屏障指令

ARM V8提供的内存屏障指令包括：
数据储存屏障（Data Memory Barrier, DMB）指令
数据同步屏障（Data Synchronization Barrier, DSB）指令
指令同步屏障（Instruction Synchronization Barrier, ISB）指令

DMB和DSB都是数据访问的内存屏障指令，ISB是指令访问相关的内存屏障指令

1 内存屏障的提供的功能

The memory barriers defined by the Armv8 architecture provide a range of functionality, including:

• Ordering of Load/Store instructions.
• Completion of Load/Store instructions.
• Context synchronization.

2 介绍DMB/DSB/ISB指令以及区别

2.1 数据存储屏障指令DMB(Data Memory Barrier)

The DMB instruction is a memory barrier instruction that ensures the relative order of memory accesses before the barrier with memory accesses after the barrier. The DMB instruction does not ensure the completion of any of the memory accesses for which it ensures relative order.
DMB指令是一种内存屏障指令，它确保屏障前的内存访问相对顺序与屏障后的内存访问相对顺序。DMB指令不确保任何它所确保相对顺序的内存访问已经完成。
保证的树内存屏障前后的内存访问指令的执行顺序，不能保证内存访问指令在内存屏障指令之前必须完成。
The basic principle of a DMB instruction is to introduce order between memory accesses that are specified to be affected by the DMB options supplied as arguments to the DMB instruction. The DMB instruction ensures that all affected memory accesses by the PE executing the DMB instruction that appear in program order before the DMB instruction and those which originate from a different PE, to the extent required by the DMB options, which have been Observed-by the PE before the DMB instruction is executed, are Observed-by each PE, to the extent required by the DMB options, before any affected memory accesses that appear in program order after the DMB instruction are Observed-by that PE.
DMB指令的基本原则是在由作为DMB指令参数提供的选项所指定的受影响的内存访问之间引入顺序。DMB指令确保由执行DMB指令的PE在DMB指令之前按程序顺序执行的所有受影响的内存访问，以及来自不同PE的内存访问（根据DMB选项的要求），在DMB指令被执行之前被PE所观察到，并且这些内存访问将被每个PE（根据DMB选项的要求）在任何在DMB指令之后按程序顺序执行的受影响的内存访问之前所观察到。
The use of a DMB instruction creates order between the Memory effects of instructions as described in the definition of Barrier-ordered-before.
使用DMB指令会在指令的内存效果之间建立顺序，如屏障排序定义中所述。
The DMB instruction only affects memory accesses and the operation of data cache and unified cache maintenance instructions. It has no effect on the ordering of any other instructions executing on the PE. A DMB instruction intended to ensure the completion of cache maintenance instructions must have an access type of both loads and stores.
DMB指令仅影响内存访问和数据高速缓存和统一高速缓存维护指令的操作。它不影响PE上执行的任何其他指令的顺序。DMB指令旨在确保高速缓存维护指令的完成，必须具有加载和存储两种访问类型。

2.2 数据同步屏障指令DSB(Data Synchronization Barrier)

这条指令可以保证任何指令都要等待DSB指令之前的存储访问操作处理完成之后才可以执行。
A DSB instruction is a memory barrier that ensures that memory accesses that occur before the DSB instruction have completed before the completion of the DSB instruction. In doing this, it acts as a stronger barrier than a DMB and all ordering that is created by a DMB with specific options is also generated by a DSB with the same options.
DSB指令是一种内存屏障，它确保在DSB指令完成之前发生的内存访问已经完成。通过这样做，它比DMB指令更强，所有由DMB指令特定选项创建的排序也可以由具有相同选项的DSB指令生成。
Execution of a DSB instruction:
执行DSB指令：
• At EL2 ensures that any memory accesses caused by Speculative translation table walks from the EL1&0 translation regime have been observed.
• 在EL2上，确保已经观察到由EL1＆0翻译管理机制引起的任何推测性翻译表访问。
• At EL3 ensures that any memory accesses caused by speculative translation table walks from the EL2, EL1&0 or EL2&0 translation regimes have been observed.
• 在EL3上，确保已经观察到由EL2、EL1＆0或EL2＆0翻译管理机制引起的任何推测性翻译表访问。

A DSB instruction executed by a PE, PEe, completes when all of the following apply:
当一个PE执行DSB指令时，该指令完成的条件为：
• All explicit memory accesses of the required access types appearing in program order before the DSB are complete for the set of observers in the required shareability domain.
对于指定的共享域内的观察者，程序中在DSB之前出现的所有特定访问类型的显式内存访问都已完成。
• If the required access types of the DSB is reads and writes, then all cache maintenance instructions, all TLB maintenance instructions, and all PSB CYNC instructions issued by PEe before the DSB are complete for the required shareability domain.
如果DSB所需的访问类型为读和写，则在所需的共享性域内，PEe在DSB之前发出的所有缓存维护指令、TLB维护指令和PSB CYNC指令都已完成。

In addition, no instruction that appears in program order after the DSB instruction can alter any state of the system or perform any part of its functionality until the DSB completes other than:
此外，在 DSB 完成之前，任何按程序顺序出现在 DSB 指令之后的指令都不能改变系统的任何状态或执行其功能的任何部分，除非：
• Being fetched from memory and decoded.
• 从内存中获取并解码指令。
• Reading the general-purpose, SIMD and floating-point, Special-purpose, or System registers that are directly or indirectly read without causing side-effects.
• 直接或间接读取通用、SIMD 和浮点寄存器、特殊寄存器或系统寄存器而不引起副作用。

2.3 指令同步屏障指令ISB(Instruction Synchronization Barrier)

该条指令会在冲刷流水线和渔区buffers后，才从高速缓存或者内存中预取ISB之后的指令。
An ISB instruction ensures that all instructions that come after the ISB instruction in program order are fetched from the cache or memory after the ISB instruction has completed. Using an ISB ensures that the effects of context-changing operations executed before the ISB are visible to the instructions fetched after the ISB instruction.
ISB指令确保在ISB指令之后按程序顺序执行的所有指令在ISB指令完成后从高速缓存或内存中获取。使用ISB可以确保在ISB之前执行的上下文更改操作的效果对在ISB指令之后获取的指令是可见的。
Examples of context-changing operations that require the insertion of an ISB instruction to ensure the effects of the operation are visible to instructions fetched after the ISB instruction are:
需要插入ISB指令以确保操作的效果对于在ISB指令后被提取的指令是可见的上下文更改操作的示例包括：
• Completed cache and TLB maintenance instructions.
• 完成的缓存和TLB维护指令。
• Changes to System registers.
• 系统寄存器的更改。
Any context-changing operations appearing in program order after the ISB instruction only take effect after the ISB has been executed.
ISB指令执行后，出现在程序顺序之后的任何上下文更改操作只有在ISB执行后才会生效。

3 内存屏障指令参数