用Verilog实现12_hour_clock(HDLbits的Count clock题)

1.topmodule top #( parameter CLKBASE = 50_000_000, //基准时钟50MHz parameter CLKDIV1K = 1_000, //分频时钟（用于扫频显示）1kHz parameter CLKDIV1 = 1 //分频时钟（用于时间累计）1Hz) ( input clk_50m, input rst_n, //复位，50/K8 input countdown_flag, //开始倒计时，51/K7 input change_time, //进行时间的设定52/K6 input clock_12_24, //修改时间12进制/24进制53/K5 input alarm_flag, //是否开启闹钟54/K4 input ctrl_hour, //控制修改小时，58/K2 input ctrl_minute, //控制修改分钟，59/K1 input ctrl_second, //控制修改秒钟，60/K0 input up_time, //时间++，49/K9 output [7:0] seg, output [7:0] word_sel, output beep_flag); //默认的起始时间 parameter para_hour = 13; parameter para_minute = 59; parameter para_second = 59; //默认的闹钟 parameter para_alarm_hour = 14; parameter para_alarm_minute = 00; parameter para_alarm_second = 10; //起始时间赋值 reg [5:0] hour, minute, second; //闹钟时间赋值 reg [5:0] alarm_hour, alarm_minute, alarm_second; //时钟开始前进 wire [5:0] new_hour, new_minute, new_second; //时间开始编码 wire [7:0] bcd_hour, bcd_minute, bcd_second; //间隔符 reg [3:0] interval; //用于存放分频时钟 wire clk_1, clk_1k; reg [31:0] clock_show; wire up_time_wire; //实例化分频模块，分频出1kHz和1Hz时钟 fre_div #(CLKBASE / CLKDIV1K) div_1k ( .clk_in (clk_50m), .rst_n (rst_n), .clk_out(clk_1k) ); fre_div #(CLKBASE / CLKDIV1) div_1 ( .clk_in (clk_50m), .rst_n (rst_n), .clk_out(clk_1) ); //对按键进行消抖，避免多次触发 xiaodou xioadou_uptime ( .clk (clk_1k), .rst_n (rst_n), .key_in (up_time), .key_flag(up_time_wire) ); initial begin hour = para_hour; minute = para_minute; second = para_second; alarm_hour = para_alarm_hour; alarm_minute = para_alarm_minute; alarm_second = para_alarm_second; end always @(posedge up_time_wire or negedge rst_n) begin if (!rst_n) begin hour <= para_hour; minute <= para_minute; second <= para_second; interval <= 15; alarm_hour <= para_alarm_hour; alarm_minute <= para_alarm_minute; alarm_second <= para_alarm_second; end else if (change_time == 1) begin case ({ ctrl_hour, ctrl_minute, ctrl_second }) 3'b001: second <= (second + 1) % 60; 3'b010: minute <= (minute + 1) % 60; 3'b100: hour <= (hour + 1) % 24; endcase end end clock clock_inst ( .clk_1 (clk_1), .rst_n (rst_n), .flag (clock_12_24), .countdown_flag(countdown_flag), .change_time (change_time), .hour (hour), .minute (minute), .second (second), .new_hour (new_hour), .new_minute (new_minute), .new_second (new_second) ); dec_to_8bcd dec_to_8bcd_inst_hour ( .DEC(new_hour), .BCD(bcd_hour) ); dec_to_8bcd dec_to_8bcd_inst_minute ( .DEC(new_minute), .BCD(bcd_minute) ); dec_to_8bcd dec_to_8bcd_inst_second ( .DEC(new_second), .BCD(bcd_second) ); always @(posedge clk_50m) begin clock_show <= {bcd_hour, interval, bcd_minute, interval, bcd_second}; end disp_scan disp_inst ( .clk_1k (clk_1k), .rst_n (rst_n), .num (clock_show), .seg (seg), .word_sel(word_sel) ); alarm alarm_inst ( .clk_50m (clk_50m), .alarm_flag (alarm_flag), .alarm_hour (alarm_hour), .alarm_minute (alarm_minute), .alarm_second (alarm_second), .current_hour (new_hour), .current_minute(new_minute), .current_second(new_second), .beep_flag (beep_flag) );endmodule2.alarmmodule alarm ( input clk_50m, input alarm_flag, //打开表示开启闹钟 //闹钟 input [5:0] alarm_hour, input [5:0] alarm_minute, input [5:0] alarm_second, //当前时间 input [5:0] current_hour, input [5:0] current_minute, input [5:0] current_second, output reg beep_flag); reg [24:0] count = 0; reg time_out; always @(posedge clk_50m) begin //打开闹钟的时候 if (alarm_flag) begin if (current_hour == alarm_hour && current_minute == alarm_minute && current_second == alarm_second) begin time_out <= 1; end else begin time_out <= 0; end end else begin //这个时候关闭闹钟 time_out <= 0; end end always @(posedge clk_50m) begin if (time_out == 1) begin if (count == 50_000_000 / (523 * 2)) begin count <= 0; beep_flag <= ~beep_flag; end else begin count <= count + 1; end end endendmodule为什么我的代码不能实现在板子上自动设置闹钟的时间