Verilog学习-05

 考研上微电子入了材料坑，开始自学verilog

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习题链接：HDLBits

三，电路

3.3，大规模电路

1000计数器

module top_module (
    input clk,
    input reset,
    output [9:0] q);

    always@(posedge	clk)begin
        if(reset==1)
            q	<=	0;
        else	begin
            if(q	==	10'b1111100111)
           	 	q	<=	0;
        	else
            	q	<=	q+1;
        end
    end

endmodule

4位移位寄存器和下行计数器

Build a four-bit shift register that also acts as a down counter. Data is shifted in most-significant-bit first when shift_ena is 1. The number currently in the shift register is decremented when count_ena is 1. Since the full system doesn't ever use shift_ena and count_ena together, it does not matter what your circuit does if both control inputs are 1 (This mainly means that it doesn't matter which case gets higher priority).

module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output [3:0] q);
    
    always@(posedge	clk)begin
        if(shift_ena==1)
            q	<=	{q[2:0],data};
        else	if(count_ena==1)
            q	<=	q-1;
    end
            
endmodule