data delay模块设计

module data_delay#(
	parameter DATA_LEN = 15,
	parameter DELAY_CLK_NUM = 28
	) 
(
	input clk,
	input[DATA_LEN - 1 : 0] data_in,
	output[DATA_LEN - 1 : 0] data_out
);

reg[DATA_LEN - 1 : 0] data_mem[0:DELAY_CLK_NUM - 1];

integer i;
always @(posedge clk) begin
	data_mem[0] <= data_in;
	for(i=1;i<DELAY_CLK_NUM;i=i+1)
		data_mem[i] <= data_mem[i-1];
end

assign data_out = data_mem[DELAY_CLK_NUM - 1];

endmodule