Vscode搭建verilog开发环境

1、Vscode下载安装

详见另一篇文章：

Vscode+Anaconda配置Python环境_vscode配置python及anaconda-CSDN博客https://blog.csdn.net/weixin_61081689/article/details/143469236?spm=1001.2014.3001.5501

2、Verilog-HDL插件

自定义代码补全：

在Vscode+Anaconda配置Python环境_vscode配置python及anaconda-CSDN博客已经指出插件的位置，只需要找到extensions\mshr-h.veriloghdl-1.15.5\snippets\verilog.json文件修改即可

修改的内容如下：

{
	"head": {
		"prefix": "head",
		"body": [
			"// +FHDR----------------------------------------------------------------------------",
			"// Project Name  : ${1:FPGA/IC_Design}",
			"// Device        : ${2:Xilinx/Synopsys}",
			"// Author        : ${3:yourname}",
			"// File Name     : ${TM_FILENAME}",
			"// Data          : $CURRENT_YEAR/$CURRENT_MONTH/$CURRENT_DATE $CURRENT_HOUR:$CURRENT_MINUTE:$CURRENT_SECOND",
			"// Description   : ",
			"                  /*",
			"                  Functions implemented",
			"                  */",
			"// -FHDR----------------------------------------------------------------------------"
		],
		"description": "Insert a module with head"
	},
	
	"module with parameters": {
		"prefix": "module #",
		"body": [
			"`timescale 1ps/1ps",
			"module ${1:moduleName} #(",
			"\tparameters\t${2:NAMEWIDTH} = $3\t//",
			") (",
			"// Input",
			"\tinput\t[${4:WIDTH} - 1 : 0]\t${5:inputname}\t//",
			"// Output",
			"\toutput reg [${6:WIDTH} - 1 : 0]\t${7:outputname}\t//",
			");",
			"\t$0",
			"endmodule"
		],
		"description": "Insert a module with parameter"
	},
	"module without parameters": {
		"prefix": "module",
		"body": [
			"`timescale 1ps/1ps",
			"module ${1:moduleName} (",
			"// Input",
			"\tinput\t[${2:WIDTH} - 1 : 0]\t${3:inputname}\t//",
			"// Output",
			"\toutput reg [${4:WIDTH} - 1 : 0]\t${5:outputname}\t//",
			");",
			"\t$0",
			"endmodule"
		],
		"description": "Insert a module without parameter"
	},
	"instantiate module": {
		"prefix": ["set module", "instantiate module"],
		"body": [
			"${1:mod_name} ${2:instance_name} (${3:.*}$0);"
		],
		"description": "set module, mod i0 (.*);"
	},
	"always combinatorial logic": {
		"prefix": "always comb",
		"body": [
			"always @(*) begin",
			"\t$1",
			"end"
		],
		"description": "always@(*)"
	},
	"always sequential logic p": {
		"prefix": "always p",
		"body": [
			"always @(posedge ${1:clk}) begin",
			"\t$2",
			"end"
		],
		"description": "always @(posedge clk)"
	},
	"always sequential logic n": {
		"prefix": "always n",
		"body": [
			"a