ADITYA JOSHI

𝐈𝐧𝐝𝐢𝐚’𝐬 𝐒𝐞𝐦𝐢𝐜𝐨𝐧𝐝𝐮𝐜𝐭𝐨𝐫 𝐇𝐢𝐫𝐢𝐧𝐠 𝐒𝐮𝐫𝐠𝐞 𝐢𝐬 𝐑𝐞𝐝𝐞𝐟𝐢𝐧𝐢𝐧𝐠 𝐂𝐚𝐫𝐞𝐞𝐫𝐬! The semiconductor industry in India is experiencing an unprecedented hiring boom — gradually chipping away at IT placements and opening exciting opportunities for engineers across domains. 🔹 End-to-end hiring: RTL/SoC design, verification, embedded systems, manufacturing (process, packaging, yield). 🔹 Freshers’ salaries: ₹6–12 LPA (vs. ₹3–4 LPA in IT). 🔹 Aggressive campus recruitment from tier-2 & tier-3 colleges, not just IITs. 🔹 Internships: ₹40k–50k/month stipends to build hands-on chip design skills. 🔹 Hiring scale: ~12,000 freshers annually (up from 8,000 last year). 🔹 Career growth: Roles extend up to ₹20–120 LPA for architects & leaders. Fuelled by global supply chain shifts, EVs, telecom, defence, and government initiatives (DLI, PLI, ECMS), this hiring surge is reshaping student aspirations, especially in ECE and core engineering branches. With India projected to hit $103B semiconductor market by 2030, this is the right time for students and professionals to align their skills with VLSI, Embedded Systems, AI/ML hardware, and semiconductor manufacturing. The future is semiconductor — and India is powering ahead as a global hub! https://lnkd.in/gKtU5Gn2 #Semiconductor #VLSI #ChipDesign #EmbeddedSystems #Electronics #SoC #SemiconductorIndia #SemiconductorJobs #SemiconductorTalent #HiringTrends #Careers #ECE #Engineering #SemiconductorEcosystem #MakeInIndia #Innovation #ElectronicsManufacturing #FutureOfWork #AI #ML #Hardware #Manufacturing #IndiaSemiconductorMission

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How to start focussing and preparing for Semiconductor and AI from 3rd year of Engineering in ECE / EEE / CSE: [1] Mathematics: Not only essential for ML and VLSI but helps in Quantum Computing as well. Key concepts: a. Probability and Statistics - Bayes theorem, variance, standard deviation, Distributions, Regression, Bias, etc. b. Linear Algebra - Eigen values, Eigen vectors, Matrix operations. c. Complex Number - Complex Plane, Polar and exponential form, Fourier transform, Euler and De Moivre's theorem, Conjugate. [2] Digital Electronics: The most basic and fundamental subject for VLSI. Key Concepts: Boolean Algebra, Combinational and Sequential Circuit, FSM, Static Timing Analysis. Not covering in depth since already covered in earlier posts. [3] Analog Fundamentals: Key concepts: a.BJT, MOSFET, CMOS, Problems on CC, CE, CB, CS, CG and CD. b. Current Mirror, Amplifier, Oscillator, Implementing stick diagrams of basic gates and custom circuits, Drain calculation, triode and saturation region. [4] Algorithms: This subject is not essential and mandatory but when I look back i personally feel that this subject is a necessity to increase the intuitive thinking and problem solving approach. Key concepts: a. Divide and Conquer, Greedy, Dynamic Programming, Sorting and Searching, travelling Salesman, Dijkstra's, kruskal, etc. b. Complexity theory - P, NP, NP Hard and NP Complete. [5] HDL Coding: Verilog - Coding guidelines, Syntax and Semantics, Coding structure. The best way to learn is to start implementing the digital blocks like multiplexer, flip flops, basic gates, counters. If you don't have any tool use edaplayground. [6] Python: Libraries: Pytorch, pyuvm, NumPy, SciPy, scikit-learn. [7] Machine Learning: Key concepts: a. Supervised, Unsupervised, Reinforcement, Neural Networks, Gradient Descent, Deep learning, Back propagation. b. Frameworks like TPU and PyTorch. [8] SystemVerilog: a. Data types, Interface, Clocking Blocks, Modport, Virtual interface, Synthesizable and Non Synthesizable construct, Testbench infrastructure. [9] Protocols: AHB, APB, FIFO to start with. Interconnect the two domains of VLSI and AI by leveraging ML for Automation in Semiconductor and debug the Chip faster. #vlsi #asic #electricalengineering #electronics

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𝐇𝐞𝐥𝐥𝐨 𝐕𝐋𝐒𝐈 𝐀𝐬𝐩𝐢𝐫𝐚𝐧𝐭𝐬 A LinkedIn connection recently attended a full-day interview for a Design Verification (DV) role at a top semiconductor company. The panels covered a broad range of topics like Verilog, SystemVerilog, UVM, assertions, coverage, and debug. Here's a detailed round-wise breakdown of the interview questions asked. ✱ 𝐒𝐭𝐞𝐩 𝟏 – 𝐑𝐞𝐜𝐫𝐮𝐢𝐭𝐞𝐫 𝐒𝐜𝐫𝐞𝐞𝐧𝐢𝐧𝐠 Walk through your resume and DV projects What protocols have you worked on (AXI, APB, etc.)? Experience with Verilog/SystemVerilog Do you know UVM or any verification methodology? Familiar with waveform debug tools (e.g., DVE, SimVision)? ✱ 𝐏𝐚𝐧𝐞𝐥 𝟏 – 𝐃𝐞𝐬𝐢𝐠𝐧 + 𝐁𝐚𝐬𝐢𝐜 𝐕𝐞𝐫𝐢𝐥𝐨𝐠 Blocking vs Non-blocking assignments Race conditions in Verilog Combinational vs Sequential always blocks FSM implementation in Verilog What is a latch? How to avoid it? Testbench components: stimulus, monitor, scoreboard Synchronous vs Asynchronous reset ✱ 𝐏𝐚𝐧𝐞𝐥 𝟐 – 𝐒𝐲𝐬𝐭𝐞𝐦𝐕𝐞𝐫𝐢𝐥𝐨𝐠 𝐂𝐨𝐧𝐜𝐞𝐩𝐭𝐬 Difference between class and struct What are mailboxes and queues? Virtual interfaces Shallow copy vs Deep copy Randomization with constraints What is a covergroup? typedef, enum, union usage this, super, static in SV ✱ 𝐏𝐚𝐧𝐞𝐥 𝟑 – 𝐔𝐕𝐌 𝐁𝐚𝐬𝐢𝐜𝐬 + 𝐀𝐫𝐜𝐡𝐢𝐭𝐞𝐜𝐭𝐮𝐫𝐞 UVM Component hierarchy UVM Factory & create method What are sequences and sequencers? Scoreboard functionality TLM ports and exports Phases of UVM (build, connect, run, etc.) UVM Configuration DB Objections in UVM ✱ 𝐏𝐚𝐧𝐞𝐥 𝟒 – 𝐀𝐬𝐬𝐞𝐫𝐭𝐢𝐨𝐧𝐬 + 𝐂𝐨𝐯𝐞𝐫𝐚𝐠𝐞 What is SVA (SystemVerilog Assertions)? Immediate vs Concurrent Assertions Covergroup vs Coverpoint Functional vs Code Coverage Cross coverage in SV How to measure coverage in UVM? Covergroup sampling and bins Writing assertions for handshake protocol ✱ 𝐏𝐚𝐧𝐞𝐥 𝟓 – 𝐏𝐫𝐨𝐭𝐨𝐜𝐨𝐥𝐬 + 𝐒𝐜𝐞𝐧𝐚𝐫𝐢𝐨𝐬 AXI Read/Write Transaction flow APB protocol differences SPI/I2C interface verification Write a monitor for a bus protocol How to handle back-to-back transactions Describe a complex scenario you’ve verified VIP (Verification IP) usage ✱ 𝐏𝐚𝐧𝐞𝐥 𝟔 – 𝐃𝐞𝐛𝐮𝐠 + 𝐏𝐫𝐚𝐜𝐭𝐢𝐜𝐚𝐥 How do you debug a failing test? How to trace an unexpected signal value in waveform? Tools you’ve used: DVE, SimVision, Verdi Race condition detection Time-consuming simulation debug strategy Handling X-propagation ✱ 𝐂𝐨𝐦𝐦𝐨𝐧 𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧𝐬 (𝐀𝐥𝐥 𝐑𝐨𝐮𝐧𝐝𝐬) Clock gating impact on verification Synchronous FIFO vs Asynchronous FIFO Gray code usage Reset synchronization UVM RAL Model Scoreboarding strategies Testplan creation and execution Multithreading in testbenches Coverage-driven verification Difference between functional and formal verification Result: Selected 👉 Join our growing VLSI community: 👉whatsapp: https://lnkd.in/gNdtCVBk 👉youtube : https://lnkd.in/gbrvuzAR 👉LinkedIn Page: https://lnkd.in/gyKg_iqs #VLSI #DesignVerification

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Open Source EDA used to build a IP company for ASIC and FPGA designs. By popular request about EDA tools we/Packet Architecs used to build our flow: - Python / myHDL for design & Verification (block & top testbenches) - We have made a couple of substancial changes to myHDL since its not great for a building large designs - cocotb (moving over from myHDL testbenches to cocotb) - Verilator (system verilog simulator, our major simulator for regressions!) - Yosys (synthesis) - gtkwave for waveform debugging - icarus verilog (another verilog simulator, but it has 4 state) - We also build a regression system over multiple servers (30+ servers) in Python - bash scripting - Latex ( for documentation) - Git - GCC first but then moved to llvm since it was faster to compile our design. - In myHDL we built a way to define register, tables which includes all the relevant documentation. Single source for all documtstion in the code. Off course a script generates the data sheets. - Look at our website for different designs ( https://www.packetarc.com/ ) We have also used Vivado (free version) since it does a pretty good job of synthesis!

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PLL (Phase-Locked Loop) and DLL (Delay-Locked Loop) are both timing circuits used for clock synchronization in digital systems, but they differ fundamentally in how they operate and what they are used for. ⸻ 🔧 PLL Types 1. PLL (APLL)-Uses analog components like VCO and charge pump; used in RF and comm systems 2. Digital PLL (DPLL)-Uses digital phase detectors and digitally controlled oscillators (DCOs) 3. All-Digital PLL (ADPLL)-Fully digital implementation; more robust in scaled CMOS nodes 4. Fractional-N PLL-Allows fractional frequency multiplication (fine resolution) 5. Integer-N PLL-Frequency multiplication by integer factors only DLL Types 1.Analog DLL-Uses analog delay lines and control loops; high resolution 2.Digital DLL-Uses discrete digital delay elements (taps); easy to integrate in digital flows 3. Hybrid DLL-Combines analog and digital delay control for better accuracy 4. Multi-Phase DLL-Generates multiple evenly spaced clock phases; used in DDR memory interfaces Remember—-> • Use PLLs when you need frequency multiplication or synthesis. • Use DLLs when you need precise phase alignment without changing frequency. PLL vs DLL: Key Differences

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20 Advanced Verilog HDL Projects with Easy Explanations – Ideal for Students and Engineers I’ve compiled a list of 20 advanced Verilog design problems with simple explanations and annotated code snippets—perfect for students and hardware enthusiasts looking to master digital design and HDL: Contact us in just a Second: https://lnkd.in/dry7JzD Pipelined 8x8 Signed Multiplier 16-to-4 Priority Encoder with Error Parametric FIFO (Queue) Universal Shift Register (Configurable) N-bit Gray Code Counter PWM Generator AXI4-Lite Slave Memory Core Traffic Light FSM with Pedestrian Input 32-bit Barrel Shifter Signed Divider (Restoring Algorithm) Dual-Port RAM UART TX/RX with Parity Clock Domain Crossing Synchronizer SPI Master with All SPI Modes FSM for Sequence Detection N-way Round Robin Arbiter Matrix Multiplication Engine CRC Generator (Configurable Polynomial) FIR Filter with Dynamic Coefficient Load Prioritized, Maskable Interrupt Controller Each problem includes a short, clear explanation and a Verilog code example, ready for anyone seeking hands-on learning or project inspiration. Feel free to DM for: The full code/explanations for any module Testbenches or detailed walkthroughs More Verilog or FPGA content! #Verilog #HDL #FPGA #DigitalDesign #EngineeringEducation #HardwareDesign #LearningResources

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