Jean-Samuel Chenard

This article advocates a systematic approach to improve NoC design quality by guiding architectural choices according to the difficulty of verification and test. The authors propose early quality metrics for added test, monitoring, and debug hardware.

Increasingly, electrical and computer engineers are making their careers in designing wireless embedded systems. This paper presents a teaching methodology and the associated laboratory setup designed to meet the needs in teaching wireless embedded systems. The courses allow the students not only to apply their previous knowledge of digital system design, computer architecture, electronic circuits, wireless networking, and software engineering, but experience actual systems engineering by… Show more

Increasingly, electrical and computer engineers are making their careers in designing wireless embedded systems. This paper presents a teaching methodology and the associated laboratory setup designed to meet the needs in teaching wireless embedded systems. The courses allow the students not only to apply their previous knowledge of digital system design, computer architecture, electronic circuits, wireless networking, and software engineering, but experience actual systems engineering by designing and implementing a large-scale team project within a semester. A flexible hardware platform was developed and was accompanied by teaching methodologies that allow quick completion of ambitious course projects in this area. Show less

Although assertions are a great tool for aiding debugging in the design and implementation verification stages, their use in silicon debug has been limited so far. A set of techniques for debugging with the assertions in either pre-silicon or post-silicon scenarios are discussed. Presented are features such as assertion threading, activity monitors, assertion and cover counters and completion mode assertions. The common goal of these checker enhancements is to provide better and more… Show more

Although assertions are a great tool for aiding debugging in the design and implementation verification stages, their use in silicon debug has been limited so far. A set of techniques for debugging with the assertions in either pre-silicon or post-silicon scenarios are discussed. Presented are features such as assertion threading, activity monitors, assertion and cover counters and completion mode assertions. The common goal of these checker enhancements is to provide better and more diversified ways to achieve visibility within the assertion circuits, which, in turn, lead to more efficient circuit debugging. Experimental results show that such modifications can be done with modest checker hardware overhead. Show less

Assertion based design, and more specifically, assertion based verification (ABV) is quickly gaining wide acceptance in the design community. Assertions are mainly targeted at functional verification during the design and verification phases. In this paper, we concentrate on the use of assertions in post-fabrication silicon debug. We develop tools that efficiently generate the checkers from assertions, for their inclusion in the debug phase. We also detail how a checker generator can be used as… Show more

Assertion based design, and more specifically, assertion based verification (ABV) is quickly gaining wide acceptance in the design community. Assertions are mainly targeted at functional verification during the design and verification phases. In this paper, we concentrate on the use of assertions in post-fabrication silicon debug. We develop tools that efficiently generate the checkers from assertions, for their inclusion in the debug phase. We also detail how a checker generator can be used as a means of circuit design for certain portions of self test circuits, and more generally the design of monitoring circuits. Efficient subset partitioning of checkers for a dedicated fixed-size reprogrammable logic area is developed for efficient use of dedicated debug hardware Show less

This paper presents techniques that enhance automatically generated hardware assertion checkers to facilitate debugging within the assertion-based verification paradigm. Starting with techniques based on dependency graphs, we construct the algorithms for counting and monitoring the activity of checkers, monitoring assertion completion, as well as introduce the concept of assertion threading. These debugging enhancements offer increased traceability and observability within assertion checkers… Show more

This paper presents techniques that enhance automatically generated hardware assertion checkers to facilitate debugging within the assertion-based verification paradigm. Starting with techniques based on dependency graphs, we construct the algorithms for counting and monitoring the activity of checkers, monitoring assertion completion, as well as introduce the concept of assertion threading. These debugging enhancements offer increased traceability and observability within assertion checkers, as well as the improved metrics relating to the coverage of assertion checkers. The proposed techniques have been successfully incorporated into the MBAC checker generator. Show less

This paper describes a wireless system infrastructure made for data collection and re-distribution in applications such as assets tracking. The system was designed to be flexible and rapidly reprogrammable, while keeping low-power and low-cost as the primary design objectives. The system comprises three distinct components - embedded nodes with user interface, network coordination and routing unit, as well as a database and dynamic Web page server. The hardware and the software were designed to… Show more

This paper describes a wireless system infrastructure made for data collection and re-distribution in applications such as assets tracking. The system was designed to be flexible and rapidly reprogrammable, while keeping low-power and low-cost as the primary design objectives. The system comprises three distinct components - embedded nodes with user interface, network coordination and routing unit, as well as a database and dynamic Web page server. The hardware and the software were designed to be modular and expandable. The complete infrastructure was built and tested in the form of a wireless conference manager. Show less

This paper presents a methodology for designing wireless nodes in which a low cost, reliable antenna is realized by printed circuit traces. We show how to combine the analysis from 2.5D and 3D EM simulators with the PCB design tools to create predictable nodes with printed antennas that meet stringent power and data transmission range goals. The presented approach is applied to the design of a IEEE802.15.4 wireless node deployed in several indoor environments.

Wireless sensor networks (WSNs) are being increasingly used in applications where low energy consumption and low cost are the overriding considerations. With increased use, their reliability, availability and serviceability need to be addressed from the outset. Conventional schemes of adding redundant nodes and incorporating reliability in control protocols can effectively improve only the reliability of the overall WSN. The availability and serviceability of WSN nodes can be addressed by… Show more

Wireless sensor networks (WSNs) are being increasingly used in applications where low energy consumption and low cost are the overriding considerations. With increased use, their reliability, availability and serviceability need to be addressed from the outset. Conventional schemes of adding redundant nodes and incorporating reliability in control protocols can effectively improve only the reliability of the overall WSN. The availability and serviceability of WSN nodes can be addressed by providing the remote testing and repair infrastructure for the individual sensor nodes that is well matched with existing on-board test infrastructure, including standard JTAG chains. We propose and evaluate scalable architectures of WSN nodes for increased availability as well as implement the proposed solutions using COTS components. Show less